Design Verification Engineer

Job Description

Job Description

Description

Senior Design Verification Engineer Job Summary We are seeking a Senior Design Verification Engineer to help verify and deliver next-generation AI SoC platforms. In this role, you will work closely with architects, RTL designers, software engineers, and system teams to ensure the correctness, performance, reliability, and safety of complex hardware systems. From block-level verification through full-chip and system-level validation, you will play a critical role in delivering high-quality silicon solutions. We are looking for engineers who enjoy understanding complex systems, uncovering corner cases, and solving challenging technical problems in a collaborative and fast-paced environment. Responsibilities Develop and execute comprehensive verification plans for IP, subsystem, and SoC-level designs. Create constrained-random, directed, and coverage-driven test environments using SystemVerilog and UVM. Develop verification components including testbenches, monitors, scoreboards, assertions, and functional coverage models. Collaborate with architects and RTL designers to define verification strategies and ensure design intent is thoroughly validated. Debug complex design and system-level issues across simulation, emulation, and silicon bring-up environments. Drive functional and code coverage closure while maintaining high verification quality standards. Verify interactions between hardware, firmware, software, and AI workloads across the platform. Support performance, reliability, and safety validation efforts for advanced AI compute architectures. Contribute to verification methodology improvements, automation, and infrastructure development. Mentor junior verification engineers and promote verification best practices across the team. Required Qualifications Bachelor's, Master's, or Ph.D. in Electrical Engineering, Computer Engineering, Computer Science, or a related field. 7+ years of ASIC or SoC design verification experience. Strong expertise in SystemVerilog and UVM verification methodologies. Experience developing constrained-random verification environments and coverage-driven verification strategies. Solid understanding of digital design, computer architecture, and RTL development. Experience debugging complex hardware issues and identifying root causes across multiple layers of the system. Proficiency with industry-standard simulation and waveform debug tools. Strong analytical, problem-solving, and communication skills. Preferred Qualifications Experience verifying AI/ML accelerators, high-performance computing systems, or data center SoCs. Knowledge of protocols such as AXI, PCIe, DDR, CXL, Ethernet, or other high-speed interfaces. Experience with formal verification, emulation, FPGA prototyping, or post-silicon validation. Familiarity with performance modeling and system-level architecture verification. Experience with embedded software, firmware, or HW/SW co-verification environments. Python, Perl, or other scripting experience for automation and workflow development.

Skills

soc design, UVM, SystemVerilog

Experience Level

Expert Level

This is a Permanent position based out of Santa Clara, CA.

The pay range for this position is $200000.00 - $400000.00/yr.

Eligibility requirements apply to some benefits and may depend on your job classification and length of employment. Benefits are subject to change and may be subject to specific elections, plan, or program terms. If eligible, the benefits available for this role may include the following: • Medical, dental & vision • Critical Illness, Accident, and Hospital • 401(k) Retirement Plan – Pre-tax and Roth post-tax contributions available • Life Insurance (Voluntary Life & AD&D for the employee and dependents) • Short and long-term disability • Health Spending Account (HSA) • Transportation benefits • Employee Assistance Program • Time Off/Leave (PTO, Vacation or Sick Leave)

This is a fully onsite position in Santa Clara,CA.

This position is anticipated to close on Jul 31, 2026.

About Actalent

Actalent is a global leader in engineering and sciences services and talent solutions. We help visionary companies advance their engineering and science initiatives through access to specialized experts who drive scale, innovation and speed to market. With a network of almost 20,000 consultants and 5,000 clients across the U.S., Canada, Asia and Europe, Actalent serves many of the Fortune 500. We are proud to be an Engineering News-Record (ENR) Top 500 Design Firm for our engineering design services and a ClearlyRated Best of Staffing® winner for both client and talent service.

The company is an equal opportunity employer and will consider all applications without regard to race, sex, age, color, religion, national origin, veteran status, disability, sexual orientation, gender identity, genetic information or any characteristic protected by law.

If you would like to request a reasonable accommodation, such as the modification or adjustment of the job application process or interviewing process due to a disability, please email View email address on ziprecruiter.com for other accommodation options.

San Francisco Fair Chance Ordinance: Pursuant to the San Francisco Fair Chance Ordinance, for all positions located in the city and county of San Francisco, we will consider for employment qualified applicants with arrest and conviction records.

Massachusetts Lie Detector: It is unlawful in Massachusetts to require or administer a lie detector test as a condition of employment or continued employment. An employer who violates this law shall be subject to criminal penalties and civil liability.

Use of Artificial Intelligence (AI): We may use Artificial Intelligence (AI) to support parts of our hiring process, including sourcing, screening, and evaluating candidates. AI helps assess applications and qualifications, but final decisions are made by our hiring team. By applying, you acknowledge and agree that your application may be reviewed using AI tools.