Senior Physical Design & Timing Engineer - High-Perf SoCs
$136k - $218.5kNVIDIA
NVIDIA is seeking a Senior Physical Design and Timing Engineer in Santa Clara, California. You will drive the physical design and timing for our state-of-the-art CPUs and GPUs, applying your expertise in Static Timing Analysis and optimization. The ideal candidate will have a background in Electrical or Computer Engineering and experience in logic synthesis. This position offers a competitive salary range from 136,000 to 218,500 USD for Level 3 positions, depending on experience. Join us in our diverse and inclusive work environment, where your skills will make a significant impact! #J-18808-Ljbffr NVIDIA
$136k - $218.5k
We are now looking for a motivated Senior Physical Design and Timing Engineer to join our dynamic and growing team. If you want... ...Drive physical design and timing of high-frequency and low-power NVIDIA CPUs, GPUs, LPUs and SoCs at block level, cluster level, and/or full...SeniorShift work$126.8k - $190.9k
...company is seeking a forward-thinking Physical Design Engineer in Cupertino, CA. The role... ...aspects of physical design, generating timing constraints, and developing high performance low power clock... ...design experience in PHY and/or SOC designs and strong knowledge of industry...Senior$130k - $220k
A technology company in Santa Clara seeks a highly skilled engineer for microarchitecture design and ASIC development. The role involves working on innovative... ...with responsibilities including RTL coding, timing closure, and design verification. Candidates should...Senior$168k - $264.5k
...looking for best-in‑class Senior Physical Design Methodology Engineer, PPA Fusion Compiler to join... ...the industry's best high speed communication devices... ...of graphics processors and SOCs. Key responsibility includes... ...methodologies for P&R, timing analysis and closure, convergence...Senior$168k - $264.5k
...Developing innovative physical design methodologies for implementation... ...processors and SOC, with emphasis on PPA... ...and turnaround time, while improving efficiency... ...Electrical or Computer Engineering (or equivalent... ...and flow development highly preferred. Proven track...Senior$116k - $189.75k
...looking for a motivated ASIC Timing Engineer to join our dynamic and... ...What you’ll be doing: Drive Physical Design and timing analysis and closure... ...NVIDIA’s GPUs, CPUs, DPUs and SoCs at block level, cluster... ...opportunity employer. As we highly value diversity in our current...- Hybrid // Physical Design Engineer-ASICs, SoCs, VLSI Physical Design Engineer-ASICs, SoCs, VLSI Full time Sunnyvale, CA Job Description: Key Responsibilities... ...and optimize low-skew, high-performance clock networks... ...and testability. Seniority level Mid-Senior level Employment...Full time
$170k - $230k
...of enabling human life on Mars. SR. SOC/ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we’re... ...grid generation, place and route, timing, noise, physical verification, electromigration... ...Pay range: Physical Design Engineer/Senior: $170,000.00 - $230,000.00 per year...SeniorPermanent employmentTemporary workWorldwideWeekend work$190.61k - $269.1k
...the Role Intel's AI SoC organization... ...accelerators. If you are an engineer with strong... ...will develop logic design, register transfer... ...ranging from RTL to timing/power convergence.... ...design integrity for physical implementation. Working... ...architectures Expertise in high-speed and low-power...SeniorLocal areaImmediate startShift work$108k - $167.5k
...As a Senior Physical Design Engineer, you will be responsible for the physical design implementation PnR... ...debugging & data analysis, scripting, STA or timing analysis. You will be reporting to... ...Netlist-to-GDS flow including block/soc-level placement, clock tree synthesis...SeniorInternshipWork at officeFlexible hours$140k - $170k
...$170,000 Credo is engineering the future of high-speed connectivity for... ...Cables(AECs) all designed for maximum performance... ...the Role As a Senior Physical Design Engineer, you... ...implementation for Credo SoC designs. This role... ...GDSII. Focus on timing, power, and area (...SeniorLocal area$163k - $237k
...qualifications Bachelor's degree in Electrical Engineering, Computer Engineering, Computer... .... 8 years of experience with physical design flow and methodologies. Experience with... ...design flow and methodologies for high-performance ASIC/SoC projects. Experience in sign-off areas...SeniorWorldwide$120k - $220k
...services. We are building a highly-advanced low Earth... ...change the design, economics, manufacturing... ...a highly experienced Senior Physical Design Engineer to join our ASIC implementation... ...of complex digital SoC designs from netlist... ..., verification, and timing teams to deliver high...SeniorFull timeWork at officeImmediate startVisa sponsorshipNight shift$120k - $200k
ASIC/SOC Silicon Physical Design Engineer Mountain View, CA MatX's mission is to make the... ...best-in-class silicon for high-performance and... ...(equivalency, extraction, timing, power estimation, EMIR, physical... ...The broad ranges for mid/senior candidates reflect greater...Full timeWork experience placementLocal area- Lightmatter is hiring a Physical Design Timing Engineer in Mountain View, California. You will help drive backend digital execution for photonics-based interconnect solutions, working alongside world-class engineers. Ideal candidates have extensive experience in ASIC STA...Senior
- ...Atheros, Inc. is seeking a senior role focused on static timing analysis, synthesis, and... ...implementation for complex WiFi SoCs. The position requires... ...with PrimeTime, Design Compiler, Genus, and multi... ...with RTL, synthesis, and physical design teams in a dynamic...Senior
$174k - $352.5k
This role has been designed as ‘Hybrid’ with an expectation... ...HPE. Job Description SoC Top-Level & block-level Physical Design Engineer Responsibilities Implement... ...clock experts. Budget timing among blocks and sub-... ...packaging is preferred. High performance and large chip...Work experience placementWork at office2 days per week- ## ASIC/VLSI Design EngineerAustin, Texas · Full-time#### About The PositionWe are... ...experienced VLSI Design Engineers/Micro-architects.As... ...to design highly sophisticated, innovative... ..., etc.* **Backend/Physical design team:** For... ...**Contribute to IP/SoC Integration*** Work...Full time
$126.8k - $190.9k
...thinking and unusually hardworking Physical Design Engineer. As a member of our wide-... ...with architecture, CAD, timing and logic design teams, with... ...phases of physical design of high performance PHY design from... ...experience in high PHY and/or SOC designs Deep Knowledge about...Relocation$220k - $350k
...Role Own Full chip and Block timing methodologies and execution to... ...accelerator silicon. Work with chip-design and software teams driving... ...tool flows to accelerate physical design timing convergence and... ...+ years of experience on very high performance designs at advanced...Permanent employmentFull timeH1bVisa sponsorshipWork visa$220k - $270k
...The company invented the world’s first 3D-stacked photonics engine, Passage™, capable of connecting thousands to millions of processors... ...of computing with light! About This Role We are hiring a Physical Design Timing Engineer to help drive backend digital execution for some of...SeniorFull timeFlexible hours- ...Position: Physical Design Engineer II (eInfochips Inc) Job Description: What You'll Be Doing:... ...implementation, encompassing synthesis, PnR, timing convergence and physical verification.... .... ~ Experience in System-on-Chip (SoC) design and implementation. ~ Expertise...Full timeTemporary workWork at office
$168k - $264.5k
Responsibilities Embedded SRAM design: transistor‑level circuit... ...supervising layout implementation, physical and logical verification, and... ...characteristics. Guiding SOC design, silicon test, and productization... ...complex circuits such as self‑timed logic and sense‑amplifiers....Senior- ...Physical Design Engineer - Location: San Jose OR Irvine, CA Our client develops specialized semiconductor... .... They are seeking an experienced Senior SoC/ASIC Physical Design Engineer to take... ...grid creation, place and route, timing analysis, noise analysis, physical verification...Full timeH1bVisa sponsorshipRelocation package
- ...will contribute to the ASIC (chip) design for high-performance network chips: AINIC... ...the architecture, IP design, Physical Design teams, and product engineers to achieve first‑pass silicon success... ...candidate will work with senior silicon design engineers. The candidate...Senior
$140k - $180k
...go, in any context, for generations to come. Reports To Interconnect Design Manager What You Will Be Doing The Mechanical Design group is seeking a Senior High-Voltage Interconnect Design Engineer to join our team. As a member of the Mechanical Design team, you will...Senior$150k - $170k
...Company) Semiconductor and Engineering Talent Acquisition... ...!!! Position: Sr. Physical Design Engineer (eInfochips Inc... ...top levels, addressing timing, congestion, IR-drop,... ...optimization, and integration of high-speed interfaces like... ...EEO/AAP policy). Seniority level Mid-Senior level...Full timeTemporary workWork at office- ...an adaptive, self-motivated design verification engineer to join our growing team.... ...contributor, you will be part of a SOC team to drive and improve... ...located in different sites/time zones. You have strong... ...medical condition, mental or physical disability, national origin...
$150k - $220k
...We are building a highly-advanced low... ...fundamentally change the design, economics,... ...We are seeking a Senior ASIC Design Engineer to join our processor... ...Collaborate with SoC architects to... ...Support synthesis and timing closure for the... ...with the physical design team · Participate...SeniorFull timeWork at officeImmediate startVisa sponsorshipNight shift$181.1k - $318.4k
...Apple products!Apple’s Silicon Engineering Group (SEG) is hiring... ...engineers for CPU block-level physical design. Description As a CPU Physical... ...aspects of CPU floorplan, timing, power, reliability, and testability... ...Experience in low power, high frequency physical design...Relocation
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