Physical Design Timing Engineer
$220k - $350kDensityAI
ITAR Notice This role involves access to ITAR-controlled information. Applicants must be U.S. persons (U.S. citizens, U.S. permanent residents, asylees, or refugees) per 22 CFR 120.62. About The Role Own Full chip and Block timing methodologies and execution to-signoff of our AI accelerator silicon. Work with chip-design and software teams driving DensityAI's AI accelerator program from first silicon through scale-out. Responsibilities Own Full chip and Block timing methodologies and execution to-signoff of our AI accelerator silicon. Use and develop AI-assisted tool flows to accelerate physical design timing convergence and signoff timelines. Qualifications Exceptional abilities across the full physical design flow (synthesis, place & route, CTS, signoff) with emphasis on timing flows and methodologies. 10+ years of experience on very high performance designs at advanced technology nodes (7nm or better) and 2.5D/3D timing flows. Hands‑on with industry-standard PD tools (Cadence Innovus, Synopsys Fusion Compiler, or equivalent) and signoff (PrimeTime, Tempus, or equivalent). Demonstrated ability to work closely with architects, RTL designers, EDA vendors, and foundries to design and sign off complex chips. Post silicon characterization and process targeting experience is highly desirable. (Optional) Multi‑die packaging (CoWoS, 2.5D / 3D), thermal / IR / EM signoff, signal integrity, or DFT‑aware physical design. Compensation Final offers depend on level, location, and skills relevant to the role. Additional compensation: equity grant per company guidelines; medical / dental / vision; 401(k); standard PTO. Visa Sponsorship DensityAI sponsors qualified candidates for H-1B, O-1, TN, E-3, and other employment-based visas, and we welcome applicants on F-1 OPT and STEM-OPT. Work authorization is required at start; we provide immigration support to secure or transfer status. Export Controls Aspects of this role may involve access to information subject to U.S. export controls (EAR/ITAR). We may discuss licensing or scope adjustments during the interview. Equal Opportunity Employer DensityAI is an Equal Opportunity Employer. We do not discriminate on the basis of race, color, religious creed, national origin, ancestry, physical or mental disability, medical condition, genetic information, marital status, sex, gender, gender identity, gender expression, age (40+), sexual orientation, military or veteran status, pregnancy, or any other status protected by law. We comply with the California CROWN Act and provide reasonable accommodations on request. Full compensation packages are based on candidate experience and relevant certifications. California Pay Range
$220,000 - $350,000 USD
#J-18808-Ljbffr DensityAI- Lightmatter is hiring a Physical Design Timing Engineer in Mountain View, California. You will help drive backend digital execution for photonics-based interconnect solutions, working alongside world-class engineers. Ideal candidates have extensive experience in ASIC STA...Suggested
$220k - $270k
...The company invented the world’s first 3D-stacked photonics engine, Passage™, capable of connecting thousands to millions of processors... ...of computing with light! About This Role We are hiring a Physical Design Timing Engineer to help drive backend digital execution for some of...SuggestedFull timeFlexible hours$136k - $218.5k
We are now looking for a motivated Senior Physical Design and Timing Engineer to join our dynamic and growing team. If you want to challenge yourself and be a part of something great, join us today! What you'll be doing Drive physical design and timing of high-frequency...SuggestedShift work$136k - $218.5k
NVIDIA is seeking a Senior Physical Design and Timing Engineer in Santa Clara, California. You will drive the physical design and timing for our state-of-the-art CPUs and GPUs, applying your expertise in Static Timing Analysis and optimization. The ideal candidate will...Suggested$116k - $189.75k
We are looking for a motivated ASIC Timing Engineer to join our dynamic and growing team. What you’ll be doing: Drive Physical Design and timing analysis and closure of NVIDIA’s GPUs, CPUs, DPUs and SoCs at block level, cluster level, and/or full chip level. Help drive...Suggested- Hybrid // Physical Design Engineer-ASICs, SoCs, VLSI Physical Design Engineer-ASICs, SoCs, VLSI Full time Sunnyvale, CA Job Description: Key Responsibilities: Block-Level Physical Design: Floorplanning & Partitioning - Define optimal floorplan with power grid, macro placements...Full time
$120k - $200k
ASIC/SOC Silicon Physical Design Engineer Mountain View, CA MatX's mission is to make the world’s best AI models run as efficiently as allowed... ...& route, clocking) and sign-off (equivalency, extraction, timing, power estimation, EMIR, physical verification) Plan and drive...Full timeWork experience placementLocal area- ...Position: Physical Design Engineer II (eInfochips Inc) Job Description: What You'll Be Doing: Execute synthesis, PNR, and STA for assigned... ...design and implementation, encompassing synthesis, PnR, timing convergence and physical verification. ~ Proficiency in...Full timeTemporary workWork at office
$170k - $230k
...ultimate goal of enabling human life on Mars. SR. SOC/ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we’re leveraging our... ...floorplanning, power/ground grid generation, place and route, timing, noise, physical verification, electromigration, voltage drop...Permanent employmentTemporary workWorldwideWeekend work$188k - $312k
...hardware innovation. Comprising brilliant engineers and visionaries, the team designs and develops advanced AI inference... ...logic, circuit, methodology, and physical design levels. Our physical design... ...partition designs to meet area, timing, and power requirements Construct...Hourly payTemporary workWork experience placementFlexible hours$174k - $352.5k
This role has been designed as ‘Hybrid’ with an expectation that you will work on average... ...SoC Top-Level & block-level Physical Design Engineer Responsibilities Implement physical design... ...collaboration with clock experts. Budget timing among blocks and sub-chips at the chip...Work experience placementWork at office2 days per week- ...Physical Design Engineer - Location: San Jose OR Irvine, CA Our client develops specialized semiconductor solutions for the edge, building processors... ..., floor planning, power grid creation, place and route, timing analysis, noise analysis, physical verification, EM/IR...Full timeH1bVisa sponsorshipRelocation package
$108k - $167.5k
...As a Senior Physical Design Engineer, you will be responsible for the physical design implementation PnR run, Performance/Power/Area (PPA) comparison... ...do synthesis, debugging & data analysis, scripting, STA or timing analysis. You will be reporting to Manager of Advanced Chip...InternshipWork at officeFlexible hours$150k - $170k
...eInfochips (An Arrow Company) Semiconductor and Engineering Talent Acquisition Professional !!! Position: Sr. Physical Design Engineer (eInfochips Inc) Experience: 10+... ...closure at both block and top levels, addressing timing, congestion, IR-drop, and physical verification...Full timeTemporary workWork at office$181.1k - $318.4k
...groundbreaking Apple products!Apple’s Silicon Engineering Group (SEG) is hiring hardworking engineers for CPU block-level physical design. Description As a CPU Physical Design... ...level teams on the aspects of CPU floorplan, timing, power, reliability, and testability Will...Relocation$126.8k - $190.9k
...opportunity for a forward-thinking and unusually hardworking Physical Design Engineer. As a member of our wide-ranging group, you will have the... ...center of a PHY design effort working with architecture, CAD, timing and logic design teams, with a critical impact on...Relocation$168k - $264.5k
...you’ll be doing: Developing innovative physical design methodologies for implementation of GPU... ...improve design performance and turnaround time, while improving efficiency and... ...need to see: MS in Electrical or Computer Engineering (or equivalent experience). Minimum 7 years...$163k - $237k
Minimum qualifications Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 8 years of experience with physical design flow and methodologies. Experience with EDA tools for physical...Worldwide$168k - $264.5k
...the world. NVIDIA is looking for best-in‑class Senior Physical Design Methodology Engineer, PPA Fusion Compiler to join our outstanding Networking... ...Participate in developing flow and tool methodologies for P&R, timing analysis and closure, convergence in IR/Signal-EM, power...- ...Job Description Job Description Physical Design Engineer Building AI chips that are hard-coded for individual model architectures.... ...to GDSII sign-off ~ Experience with back-end design and timing closure on 3nm-7nm ~ Experience with UPF-based low power...
$2,000 per month
...frontier intelligence. We co-design chips, racks, software, and manufacturing... ...and staffed by leading engineers, Etched is redefining the... ...is looking for exceptional Physical Design engineers to join our... ...implementation and verification, drive timing closure and PPA optimization,...Work at officeRelocation package$120k - $220k
...system that will fundamentally change the design, economics, manufacturing and service... ...seeking a highly experienced Senior Physical Design Engineer to join our ASIC implementation team.... ...with front-end design, verification, and timing teams to deliver high-quality,...Full timeWork at officeImmediate startVisa sponsorshipNight shift$163k - $237k
Physical Low Power Validation Engineer Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer... ...or low-power signoff in an ASIC design environment. Experience in static... ...and an understanding of standard cell timing, hierarchical construction, and...Worldwide$126.8k - $190.9k
A leading technology company is seeking a forward-thinking Physical Design Engineer in Cupertino, CA. The role includes contributing to all aspects of physical design, generating timing constraints, and developing high performance low power clock networks. Ideal candidates...- ## ASIC/VLSI Design EngineerAustin, Texas · Full-time#### About The PositionWe are looking for talented and experienced VLSI Design Engineers/Micro-architects.As an VLSI Digital Design Engineer/Micro... ...ATPG, BIST, etc.* **Backend/Physical design team:** For floorplanning,...Full time
$190k - $230k
...builds the world’s largest AI chip, 56 times larger than GPUs. This... ...Responsibilities Work with architects, designers, post‑silicon and software engineers to ensure a high‑quality design that... ...including architecture, RTL design, physical design, firmware, and validation....- Tesla Motors, Inc. is seeking a Staff Physical Design Engineer to own the physical implementation of complex 3D IC stacks, from floorplan to signoff, using advanced hybrid bonding. You will tackle die-to-die integration and optimize layouts to meet aggressive performance...
$100k
...contributors of all seniorities. Tenstorrent is seeking a Physical Design Engineer to lead cross‑functional efforts to solve complex physical design... ...flows to improve engineering efficiency, turnaround time, and QoR. Optimize EDA tools and custom CAD flows using data...Permanent employment$92k
...highly talented and self- motivated Design Verification Engineer to join it in advancing the technological... ...REQ ID: 118963 Position Type: Full Time We are seeking a highly motivated... ...origin, pregnancy, sexual orientation, physical disability or genetic information,...Full timeLocal area$100k
...hard problems. We are growing our team and looking for contributors of all seniorities. Tenstorrent is seeking a SoC Physical Design Verification Engineer to drive full‑chip signoff and ensure manufacturable, high‑quality silicon across advanced technology nodes. You’ll...Permanent employment
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