Senior ASIC Design Engineer, Memory Controller & RTL
$136k - $265kNVIDIA Gruppe
NVIDIA Gruppe is seeking a Senior ASIC Design Engineer for its Memory Controller team in Santa Clara, California. This role involves collaboration with architects and engineers to design and verify micro-architectures for memory subsystems. The ideal candidate will have experience in ASIC design, strong knowledge of Verilog/SystemVerilog, and programming skills. Compensation ranges from $136K to $265K based on experience, with additional equity and benefits. #J-18808-Ljbffr NVIDIA Gruppe
Vacancy posted 4 days ago
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