Senior Physical Design Engineer

Credo is engineering the future of high-speed connectivity for the AI-driven world. With a deeply rooted legacy of innovation and a passion for solving the most complex networking challenges, we deliver industry-leading solutions that power the next generation of cloud, AI, and hyperscale data centers. Credo is pioneering a systems-level approach to connectivity, integrating hardware, software, and architecture to deliver holistic solutions. This strategy not only differentiates us in the market but also creates significant value for our customers by accelerating deployment, improving performance, and reducing complexity across their infrastructure. At Credo, you’ll be part of a team of world-class technologists and engineers that thrive on pushing the limits of what’s possible for some of the world’s most important companies. Our portfolio includes cutting edge solutions including our software, optical DSPs, PCIe/CXL products, SerDes IP, and advanced Active Electrical Cables (AECs) all designed for maximum performance, energy efficiency, and scalability. We foster a culture of technical excellence, collaboration, and continuous learning, where your ideas can shape the future of connectivity. From silicon architects to systems engineers, every role at Credo contributes to solving real-world problems at scale. Join us and help us architect the next generation of disruptive networking technologies — because at Credo, We Connect. About the Role As a Senior Physical Design Engineer, you will manage all aspects of physical design and implementation for Credo SoC designs. This role involves close collaboration with the local frontend team and PD/integration teams in China and Taiwan to ensure successful tapeouts. Responsibilities Lead and drive top-level, IP, and block-level physical implementation from RTL to GDSII. Focus on timing, power, and area (PPA) optimization for high-speed SerDes and interconnect subsystems. Establish and maintain physical design methodologies, flow automation, chip floorplanning, power/clock distribution, chip assembly, P&R, and timing closure. Perform static timing analysis, power and noise analysis, and physical verification. Collaborate closely with frontend and integration teams to ensure successful tapeouts. Basic Qualifications BS/MS in EE/CS with 10+ years of hands-on experience in back-end physical design and verification. Familiar with hierarchical physical design strategies, methodologies. Proven track records of handling chip level P&R independently and taping out complex SOC chips under tight schedule pressure. Experience with 5nm and lower technology nodes. Strong proficiency with EDA tools such as Cadence Innovus and Synopsys Fusipn Compiler. Solid knowledge on static timing analysis (PrimeTime/Tempus), EM/IR-Drop/crosstalk analysis (PTSI/Voltus/Redhawk), extraction (Quantus/StarRC). Preferred Qualifications Familiarity with DRC, Antenna, LVS, ERC tools like Calibre. The base salary range for this position is $140,000 – $170,000 a year. The base salary ultimately offered is determined through a review of education, experience, training, skills, qualifications, and location. This position is also eligible for a discretionary bonus, equity and a full range of medical and other benefits. Credo is an Equal Opportunity Employer. We are committed to creating an inclusive environment for all employees and welcome applicants from diverse backgrounds without regard to race, color, religion, gender, sex, sexual orientation, national origin, genetic information, age, disability, veteran status, or any other legally protected basis. If you have a disability or special need that requires accommodation to navigate our website or complete the application process, email View email address on click.appcast.io. #J-18808-Ljbffr