TPU RTL Design Engineer

corporate_fare Google place Sunnyvale, CA, USA Qualifications Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. 2 years of experience in ASIC RTL design, with a focus on clocking, reset, or timing‑critical RTL development. Experience with digital clock control circuits, including clock dividers, glitch‑free muxes, and clock gating. Experience in SystemVerilog for creating microarchitecture specifications and synthesizable RTL. Experience using Python, Tcl, or Perl for automating design tasks and data analysis. Preferred qualifications Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture. 5 years of experience with high‑performance ASIC design in Phase‑Locked Loop, Frequency‑Locked Loop, and Delay‑Locked Loop integration. Experience implementing clock skipping, Dynamic Voltage and Frequency Scaling (DVFS), and fine‑grained clock gating for low‑power SoC optimization. Knowledge of processor design or accelerators and of high‑performance and low power design techniques. Proficiency in Python or Perl for automating design scripts and analyzing complex clock‑tree data. Understanding of clock distribution challenges, including jitter, skew management, and duty‑cycle distortion. Responsibilities Work independently to create and review clock control subsystem's design micro‑architecture specifications. Develop SystemVerilog RTL to implement logic for ASIC products according to established coding and quality guidelines. Work with architecture and power teams to evaluate features and their impact. Work with Design Validation (DV) teams to create test plans to verify, and debug design RTL. Work with physical design teams to ensure design meets physical requirements and timing closure. About the job In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting‑edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML‑driven systems. Benefits US: $138000 - $198000 (USD) + 15% bonus target + equity + benefits Individual pay is determined by factors including job‑related skills, experience, and relevant education or training. Equal Opportunity Employer Google is proud to be an equal opportunity and affirmative action employer. We are committed to building a workforce that is representative of the users we serve, creating a culture of belonging, and providing an equal employment opportunity regardless of race, creed, color, religion, gender, sexual orientation, gender identity/expression, national origin, disability, age, genetic information, veteran status, marital status, pregnancy or related condition (including breastfeeding), expecting or parents‑to‑be, criminal histories consistent with legal requirements, or any other basis protected by law. See also Google's EEO Policy, Know your rights: workplace discrimination is illegal, Belonging at Google, and How we hire. #J-18808-Ljbffr Google Inc.