Senior STA Signoff Methodology Engineer
$168k - $264.5kNVIDIA
NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It’s a unique legacy of innovation that’s fueled by great technology—and amazing people. Today, we’re tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what’s never been done before takes vision, innovation, and the world’s best talent. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join the team and see how you can make a lasting impact on the world. We are seeking an innovative Senior STA Signoff Methodology Engineer to help drive sign-off strategies for the world's leading GPUs, CPUs, LPUs and SoCs. This position is a broad opportunity to optimize performance, yield, and reliability through increasingly comprehensive modeling, insightful analysis, and automation. This work will influence the entire next generation AI landscape through critical contributions across NVIDIA's many product lines. We have crafted a team of highly motivated people whose mission is to push the frontiers of what is possible today and define the platform for the future of computing. If you are fascinated by the immense scale of precision, craftsmanship, and artistry required to make billions of transistors function on every die at technology nodes as deep as 3nm and beyond, this is an ideal role. What You'll Be Doing Run large-scale SPICE simulations and STA experiments to model the impact of advanced technologies on chip timing. Develop STA and PNR flows and recommendations addressing aging, self-heating, thermal effects, IR drop, electro migration, and other advanced-node physical effects. Collaborate with technology leads, physical-design engineers, and timing engineers to define and deploy sophisticated timing-signoff strategies for extraordinary silicon performance. Develop tools and methodologies that improve design performance, predictability, and silicon reliability beyond the capabilities of standard EDA tools. Work across STA, constraints, and timing and power optimization. Perform extensive data analysis using Python, JMP, or similar tools to improve STA-to-silicon correlation. What We Need To See MS in Electrical or Computer Engineering, or equivalent experience, with 8 years of experience in ASIC design and timing. Solid understanding of RC extraction, device physics, STA methodologies, and EDA-tool limitations. Proven foundation in the mathematics and physics underlying electrical design. Experience with low-power techniques, including multi-Vt design, clock gating, power gating, activity-based power analysis, DVFS, and CDC. Understanding of signal and power integrity, crosstalk, electromigration, noise, OCV, timing margins, clock jitter, and IR drop. Understanding of standard-cell, memory, and I/O IP modeling and their use in ASIC flows. Hands‑on experience with advanced FinFET and emerging CMOS technologies at 5 nm, 3 nm, 2 nm, and beyond. Familiarity with industry-standard ASIC tools such as PrimeTime, ICC2, RedHawk, and Tempus. Strong communication skills and a collaborative working style. Ways To Stand Out From The Crowd Familiarity with 3D IC integration, die stacking and packaging, self-heating, and their impact on timing closure. Strong data-analysis and modeling skills employing Python, JMP, or similar platforms. Proficiency in Tcl and Python; C++ experience is a plus. NVIDIA is widely considered one of the technology world’s most desirable employers. We have some of the most forward-thinking and talented people in the world working for us. If you’re an engineer who thinks in systems, takes pride in designing things that last, and wants to see the silicon your work helps produce - we want to hear from you. Widely considered to be one of the technology world’s most desirable employers, NVIDIA offers highly competitive salaries and a comprehensive benefits package. As you plan your future, see what we can offer to you and your family Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 168,000 USD - 264,500 USD for Level 4, and 196,000 USD - 310,500 USD for Level 5. You will also be eligible for equity and benefits. Applications for this job will be accepted at least until August 24, 2026. This posting is for an existing vacancy. NVIDIA uses AI tools in its recruiting processes. NVIDIA is committed to fostering an inclusive work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.
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#J-18808-Ljbffr NVIDIA- NVIDIA is seeking an innovative Senior STA Signoff Methodology Engineer in Austin, TX. You will drive sign-off strategies for GPUs/CPUs/SoCs, optimize performance, yield, and reliability through advanced modeling, analysis, and automation. You will collaborate with design...Senior
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...for a Principal Application Engineer responsible for providing pre... ...the Digital Implementation and Signoff tools. The candidate will... ...benchmarks, product demonstrations, methodology consultations and product... ...signoff expertise, advanced node STA, UPF & constraints debugging,...Suggested$121.8k - $182.6k
Company: Qualcomm Technologies, Inc. Job Area: Engineering Group, Engineering Group > ASICS Engineering General Summary: Senior Emulation Performance Methodology & Debug Engineer Minimum Qualifications Bachelor's degree in Science, Engineering, or related field and 4+...SeniorWork experience placementWork from homeNight shift- NVIDIA is seeking a Senior CPU Design Methodology Engineer in Austin, TX to define scalable SOC methodologies and tools for front-end chip implementation. You will work with ASIC, Physical Design, CAD, and software teams to optimize RTL quality and automation. You will...Senior
- ...experienced ASIC Timing Analyst responsible for end-to-end timing signoff, constraints creation, and validation across frontend, IP, DFT... ...flagship SoCs. You will work with implementation owners and Full-Chip STA teams, generate timing fixes, and drive automation strategies to...
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...now looking for a motivated ASIC Timing Engineer to join our dynamic and growing team. If... ...convergence flows in collaboration with methodology teams. What We Need To See BS (or equivalent... ...with 3 years’ experience in Timing and STA Hands-on experience in full-chip/sub-...Senior- ...looking for an experienced ASIC Verification Engineer who is passionate about solving complex... ...coverage closure and verification signoff activities. Debug challenging RTL, protocol... ...engineers contributing to verification methodology improvements across the organization. Why...SeniorWorldwide
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...Senior Hardware Design Engineer The era of pervasive AI has arrived. In this era, organizations will... ...including AI and automation in EDA tool methodologies. Required Qualifications... ...synthesis tools and Static Timing Analysis (STA). Proficiency with industry-...SeniorWork at officeLocal area- ...Senior Signal Integrity EngineerFrom applied research to advanced engineering, the Engineering Technologist team has the expertise to shape ground-breaking products,... ...Drive pre-layout and post-layout simulation methodologies and sign-off criteria across the organization...Senior
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...About the Role We are looking for a Senior RTL Design Engineer / Lead to own micro‑architecture, RTL... ...ensure RTL is robust, reusable, and signoff‑ready. Generate and refine timing... ...‑power‑domain designs and low‑power methodologies. Prior silicon debug experience (post...SeniorTemporary workWorldwide$106.5k - $162k
Overview of Role As a Sr. Physical Design Engineer, you will be responsible for the... ...synthesis, floorplan, place and route, CTS, STA, and signoff. You will be reporting to Manager of... ...technology Low-power implementation methodology Advanced timing signoff methodology Able...SeniorWork at office$168k - $264.5k
...looking for a Full-Chip RTL Integration Engineer to join our dynamic and growing FE-ASIC... ...requirements are met. Support design signoff activities and ensure smooth handoff across... ...designs. Strong understanding of DFT methodologies including Scan, ATPG, MBIST, LBIST,...Senior$167.7k - $245.2k
...models, bare die & stacked die, driving re-usable test and debug methodologies and standards. The job requires the candidate to have the... .... Minimum Qualifications Bachelor’s in Electrical Engineering or equivalent with at least 7+ years (or Master's with 4+ years...SeniorFull timeTemporary workLocal areaFlexible hours3 days per week$168k - $264.5k
...today. NVIDIA’s DFX team is looking for an exceptional DFT Engineer to help shape the future of compute. As stewards of the entire... ...you'll be doing: Develop and deploy Industry-leading test methodologies on NVIDIA’s next-generation silicon platforms....SeniorFull time$80k - $400k
...with team members, or directly with our clients. Self driven engineers who love to identify and experiment with new approaches,... ...development, including working in teams ~ Experience with agile methodologies such as Scrum, Kanban or XP ~ Deep knowledge in the...SeniorInternshipWork at officeRemote workFlexible hours- ...Description The Role SiFive is looking for a Senior Design Verification Engineer to drive functional verification of... ..., risks are identified early, and signoff quality is achieved with strong... ..., and contribute reusable methodology and infrastructure to the broader CPU...Senior
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...and Impact Join Intel's mission to engineer world-changing technology as a Senior EDA Tools Hardware Engineer. We... ...role focuses on characterization methodology, CAD infrastructure, automation, and... ...with custom circuit, memory design, STA, and methodology teams to enable...SeniorInternshipLocal areaShift work- ...Description SiFive is looking for a Senior Staff Design Verification Engineer to lead verification of a next‑... ...through subsystem integration and signoff. Define verification strategy, test... ...and test content. Contribute to methodology and infrastructure improvements that...SeniorImmediate start
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As a Senior DFT Engineer - Post-Silicon , you will take pioneering DFT capabilities beyond implementation—connecting silicon behavior, test... ...with clear metrics/what-if analysis. Define and improve methodologies for silicon bring-up, failure analysis, test-content validation...Senior- ...for the Texas region trenchless market Perform geotechnical engineering analyses and design calculations for trenchless, tunnels, shafts... ...and design experience with trenchless construction methodologies such as HDD, microtunneling, auger boring is an asset Requirements...SeniorFull timeTemporary workLocal areaFlexible hours
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A well-funded hardware startup in Austin, Texas, is looking for an experienced DFT Engineer to innovate design-for-test methodologies for advanced digital and mixed-signal SoCs. The role requires 5+ years in DFT with hands-on experience in silicon bring-up and DFT validation...Senior- ...Advanced Technology Group is seeking a Full-Chip RTL Integration Engineer to join the FE-ASIC development team in Austin. You will lead... ...Verification, DFT and Physical Design to drive system-level integration, signoff, and smooth handoff across stages, with #J-18808-Ljbffr NVIDIASenior
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