Senior ASIC Verification Lead for SoC Bring-up
$210.6k - $305.1kCisco
Cisco Systems, Inc. is seeking an ASIC Design Verification Engineer in San Jose, California. You will architect and develop DV infrastructure, create comprehensive test plans, and ensure robust verification for complex chips. The ideal candidate has extensive experience with Verilog, SystemVerilog, and UVM. The starting salary range is between $210,600 and $305,100, alongside comprehensive benefits including medical, dental, vision, and 401(k) matching. #J-18808-Ljbffr
Vacancy posted 12 hours ago
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