Senior ASIC Verification Engineer (SystemVerilog & UVM)
Broadcom Corporation
Broadcom Inc. is looking for a Verification Engineer in San Jose, California. The successful candidate will develop verification plans and build verification environments for advanced ASIC products. Applicants should have substantial experience in verification methodologies and programming skills in Python and C/C++. This position includes a comprehensive benefits package and competitive salary. #J-18808-Ljbffr
- ...innovative high-tech startup in Santa Clara seeks a Senior Design Verification Engineer to architect and develop verification... ...candidate will have extensive experience in ASIC verification, strong skills in SystemVerilog and UVM, and a passion for solving complex problems....Senior
$116k - $189.75k
...NVIDIA Corporation in Santa Clara is seeking an ASIC Clocks Verification Engineer to collaborate with ASIC designers and verification engineers... ...Electrical Engineering and practical experience with SystemVerilog, UVM, and strong scripting skills in Python or Perl. The position...Senior- ...NVIDIA Corporation is hiring a Senior ASIC Verification Engineer in Santa Clara, California. This position involves verifying designs and implementations... ...+ years of relevant experience, and be proficient in SystemVerilog and UVM. The role provides a competitive salary range of $136...Senior
$145k - $286k
1000 Micron Technology, Inc. is hiring a Staff ASIC Design Verification Engineer in San Jose, California. The role involves defining and improving... ...of experience in verification, with strong skills in SystemVerilog and UVM methodology. The compensation ranges from $145,000 to...Senior$136k - $218.5k
Senior ASIC Verification Engineer page is loaded## Senior ASIC Verification Engineerlocations: US, CA, Santa Claratime type: Full timeposted on... ...Oriented Programming principles and proficient in SystemVerilog/UVM.* Familiarity with memory subsystem concepts such as memory...Senior- ...impact - we want to talk to you. What you’ll do As a Senior ASIC Design Verification Engineer, you will be responsible for verifying critical... ...practices. Technical Mastery: Advanced skills in SystemVerilog/Verilog, UVM methodology, and C/C++ programming, including embedded...SeniorFlexible hours
- ...A leading technology company is seeking a Senior Verification Engineer to join their multi-media IP team. The ideal candidate will have at least 5 years of design verification experience, particularly in verifying sophisticated IPs using System Verilog. Responsibilities...Senior
- ...A leading technology company in Santa Clara is looking for a Design Verification Engineer to ensure the functionality and performance of their SOCs. The role involves developing test plans, collaborating with design teams, and verifying various hardware components. The...Senior
$136k - $218.5k
...boundaries of computing innovation. Our ASIC Verification Engineers focus on developing the world’s top SoCs and GPUs. Joining us as a Senior ASIC Verification Engineer - GPU means working... ...verification methodologies such as UVM or equivalent. Understand the design and...Senior$136k - $264.5k
NVIDIA Gruppe is seeking a Senior Design Verification Engineer to enhance efficiency in their High Speed IO... ...of computer architecture, ASIC design, and verification tools, alongside... ...alongside proficient programming skills in SystemVerilog and Python. The position offers a...Senior- ...A leading engineering company is seeking a highly skilled FPGA Verification Engineer in Santa Clara, CA. You will verify complex FPGA designs, collaborating... ...experience in FPGA and strong proficiency in UVM and SystemVerilog. This is a full-time onsite role, requiring a...Full time
- ...Role NVIDIA is seeking an outstanding ASIC Verification Engineer to verify the design and... ...Oriented Programming with C++ and/or SystemVerilog. Exposure to design and verification... ...like Debussy, GDB) and methodologies (UVM or equivalent). Passion for debugging...
- ...GPU clocks group is looking for an exceptional ASIC Clocks Verification Engineer. The team is responsible for crafting all... ...equivalent experience). Practical experience with SystemVerilog and Universal Verification Method (UVM). Experience with design verification, logic...
- ...Expertise in ASIC/SoC verification using HVLs. Knowledge of networking protocols will be an addedadvantage. Expertise in SystemVerilog, System C,Verification Methodologies such as OVM,UVM,etc. Should have worked on at least one full-chip or module-level verification using...Senior
$136k - $218.5k
...this position, you will be responsible for verification of high-speed coherent interconnect... ...developing TB's from scratch using SV and UVM methodology is desired. C++ programming... ...required. A history of mentoring junior engineers and interns a huge plus. To learn more about...Senior- ...want to talk to you. What you’ll do: As a Senior ASIC Design Engineer, you will be responsible for the design, development, and verification of blocks that will run the smallest to... ...design. Strong knowledge of Verilog/SystemVerilog for RTL design Knowledge of modern ASIC...SeniorFlexible hours
$149.1k - $215k
...industry. Role Sr. Debug Design Verification Engineer. You will be responsible for... ...and test benches using UVM methodology. Capacity could... ...of experience with complex ASIC designs and/or verification.... ...8+ years of experience with SystemVerilog language. 8+ years of experience...SeniorLocal area$168k - $264.5k
...Senior Verification Engineer - Hardware page is loaded Senior Verification Engineer... ...SpeedBridges, Accelerated UVM Testbenches). Bring up SOCs... ...Verilog and/or VHDL, C/C++ and SystemVerilog. Experience with UVM... ...law. Similar Jobs (5) Senior ASIC Design Engineer - Hardware...SeniorFull timeWorldwideFlexible hours$156k - $229k
...Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science... ...8 years of experience with design verification. Experience with SystemVerilog. Preferred qualifications:... ...exceptional verification. Using your UVM and SystemVerilog coding and problem...SeniorFull timeWorldwide$116k - $189.75k
...GPU clocks group is looking for an exceptional ASIC Clocks Verification Engineer. The team is responsible for crafting all... ...equivalent experience).* Practical experience with SystemVerilog and Universal Verification Method (UVM).* Experience with Design Verification, Logic...- NVIDIA Gruppe in Santa Clara is looking for a Senior ASIC Verification Engineer to join our ASIC Verification team. This role involves verifying the industry's leading GPUs and collaboration with various teams to ensure the design's correctness. The ideal candidate will...Senior
- ...seeking a talented and detail-oriented ASIC Design Verification (DV) Engineer to join our chip design team. You'... ...using advanced methodologies like UVM (Universal Verification Methodology... ...verification environments using SystemVerilog and UVM. Verification Languages: Expertise...
- ...Technology, Inc. is seeking a New College Graduate for the Design Engineer position in San Jose, California. The role involves developing testbench content, supporting verification environments using SystemVerilog, and improving design efficiency through automation tools....
- ...looking for a skilled Design Verification Engineer to join the Network... ...This role involves developing UVM-based testbench architectures... ...verification efforts on complex ASIC designs. The ideal candidate should have expertise in SystemVerilog, strong debugging skills, and...Senior
- A leading technology company is seeking a Senior Design Verification Engineer in Santa Clara, CA. This role involves improving verification flows, collaborating... ...ideal candidate will possess significant experience in ASIC design, verification methodology, and programming. The...Senior
$138k - $198k
...Qualifications Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science,... .... 4 years of experience with design verification. Experience in verifying digital logic at RTL using SystemVerilog/UVM for ASICs. Preferred qualifications Master's...Full timeWorldwide$138k - $198k
ASIC Design Verification Engineer, AI and Infrastructure Qualifications Bachelor's degree in Electrical Engineering... ...verification. Experience with SystemVerilog/Verilog. Preferred qualifications:... ...using SystemVerilog and UVM, or formally verify designs with SVA...Full timeWorldwide$153.2k - $229.8k
...Qualcomm Technologies, Inc. Job Area: Engineering Group, Engineering Group ASICS Engineering General Summary:... ...you come in as an ASIC Design Verification Engineer. The team is responsible... ...methodology such as SystemVerilog-UVM, coverage development, assertion...Work experience placement$85 - $107 per hour
...Downtown Boulder Partnership is seeking a Senior Design Verification Engineer to lead verification teams in Santa Clara, CA. This role involves defining verification plans, creating UVM/SystemVerilog testbenches, and ensuringdesign quality. The ideal candidate will possess...Senior$138k - $198k
Google Inc. seeks an ASIC Design Verification Engineer in Sunnyvale, CA, to shape future AI/ML hardware acceleration. You will drive TPU technology... ...of design verification experience, particularly in SystemVerilog and UVM. This full-time role offers a competitive salary...Full time
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