Sign up to access all features of our service.
  • Job search
  • Favorites
  • Create a CV
    New
  • Salaries
  • Subscriptions

Packaging Design Engineer

$144k - $209k

Google

Minimum Qualifications Bachelor's degree in Packaging Engineering, Mechanical Engineering, Industrial Engineering, a related engineering field, or equivalent practical experience. 8 years of experience in hardware product packaging and structural design. Preferred Qualifications 8 years of experience in hardware or industrial packaging design. Proven ability to work autonomously, take complete ownership of projects, and deliver results with minimal guidance. Natural innovator with a track record of thinking outside-the-box to design creative solutions for complex structural, space, or material constraints. About The Job Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. The Packaging Design Engineer serves as the critical technical link between advanced hardware engineering and global operations. In this role, you will lead the end-to-end structural development, mechanical validation, and technical execution of protective packaging systems designed specifically for complex, high-value, and shock-sensitive hardware infrastructure. Operating within a changing New Product Introduction (NPI) framework, you will own the entire packaging development lifecycle from initial concept phase through to global mass production. You will cross-functionally collaborate with product designers, supply chain partners, and manufacturing facilities to translate complex product fragility requirements into highly reliable, scalable, and freight‑efficient architectures. You will bring a data‑driven approach to structural design, utilizing predictive engineering tools alongside physical testing to eliminate transport risks. You will act as an internal advocate for sustainable engineering, continuously identifying opportunities to reduce carbon footprints, minimize material waste, and optimize cube usage without compromising product safety. Ultimately, your work ensures that our next‑generation physical infrastructure transitions seamlessly and reliably from factory floors to global deployment sites around the world. The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide. We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting‑edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world‑leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. The US base salary range for this full‑time position is $144,000-$209,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job‑related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process. Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google. Responsibilities Utilize advanced Three‑Dimensional/Two‑Dimensional Computer‑Aided Design software (SolidWorks, Artios CAD, Creo, etc.) to architect complex structural packaging solutions and generate precise technical drawings, assembly instructions, and cushion layouts. Manage technical documentation within Product Lifecycle Management systems. Own the release of Bills of Materials, component specifications, and Engineering Change Orders/Requests. Apply strict Design for Manufacturing principles to optimize pack‑out workflows, ensuring packaging designs can be assembled efficiently, safely, and seamlessly on global manufacturing lines. Serve as the Subject Matter Expert on packaging material properties, driving the integration of novel, high‑performance, and sustainable or recyclable materials to meet corporate environmental goals. Conduct Finite Element Analysis and dynamic simulations to evaluate drop impact, velocity, and vibration stress distribution, accelerating development and reducing physical prototyping loops. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form. #J-18808-Ljbffr Google

Vacancy posted 1 day ago
Similar jobs that could be interesting for youBased on the Packaging Design Engineer in Sunnyvale, CA vacancy
  •  ...Position Overview We are seeking a highly motivated Chiplet Package Design Engineer to drive the development of advanced packaging solutions for next-generation semiconductor products. This role focuses on 2.5D and 3D heterogeneous integration , enabling high-performance... 
    Suggested
    Full time

    Rapidus Corporation US

    Santa Clara, CA
    3 hours ago
  • $144k - $209k

    Google Inc. in Sunnyvale is seeking a Packaging Design Engineer to lead the development of innovative packaging solutions for high-value hardware. This role involves collaborating with diverse teams to ensure designs are efficient, sustainable, and meet stringent safety... 
    Suggested

    Google Inc.

    Sunnyvale, CA
    4 days ago
  • $156k - $229k

     ...Apply Bachelor's degree in Mechanical, Material, Electrical Engineering, Technology, Science, a related field, or equivalent practical experience. 5 years of experience in chip package substrate design using Cadence APD (Allegro Package Designer) or Mentor Expedition... 
    Suggested
    Full time
    Worldwide

    Google Inc.

    Mountain View, CA
    5 days ago
  • $144k - $209k

     ..._fare Google place Sunnyvale, CA, USA Bachelor's degree in Packaging Engineering, Mechanical Engineering, Industrial Engineering, a related engineering...  ...of experience in hardware product packaging and structural design. Preferred qualifications: 8 years of experience in... 
    Suggested
    Full time
    Worldwide

    Google Inc.

    Sunnyvale, CA
    4 days ago
  • $144k - $209k

    Google is seeking a Packaging Design Engineer in Sunnyvale, California, to innovate packaging solutions for cutting-edge products. This role requires ownership of the entire packaging development lifecycle, from initial concept to mass production. You will collaborate with... 
    Suggested

    Google

    Sunnyvale, CA
    2 days ago
  •  ...resilience, and productivity. We’re looking for a smart, driven engineering professional to join our infrastructure team and help...  ...environment across the company. About the role: As a SI/PI Package Design Engineer focused on 224G Ethernet switches, your role is critical... 
    Full time

    Upscaleai

    Santa Clara, CA
    4 days ago
  •  ...Position Overview We are seeking a highly capable Customer Package Design Integration Engineer (2.5D / 3D Packaging) to ensure the successful execution of customer chiplet-based product development using Rapidus advanced packaging technologies. This role serves... 
    Full time

    Rapidus Corporation US

    Santa Clara, CA
    3 hours ago
  • $160k - $210k

     ...Taara here. About the Role The successful candidate will design and implement packaging solutions for micro-optic assemblies of Si photonic and...  ...this happen. What you should have M.S. in Electrical Engineering, Applied Physics or related field Five (5) or more years... 
    Full time

    Taara

    Sunnyvale, CA
    5 days ago
  •  ...Our client is seeking an experienced Package Design Engineer for complex flip-chip-BGA packages for industry-leading ASICs with high-speed SerDes and RF/microwave communications A/D D/A converters (ADC & DAC). You will be part of a worldwide R&D team developing... 
    Worldwide

    Advanced Technology Search

    San Jose, CA
    1 day ago
  • $157k - $235k

     ...Category Engineering Hire Type Employee Job ID 13846 Base Salary Range $157000-$23500...  ...cars to learning machines. We lead in chip design, verification, and IP integration,...  ...professional with a passion for advanced silicon package design and a proven track record in... 
    Remote work

    Synopsys Inc

    Sunnyvale, CA
    a month ago
  • $134.39k - $201.3k

     ...Generative Ai Engineer Marvell's semiconductor solutions are the essential building blocks...  ...Contribute to the development and packaging of optical components and sub-assemblies...  ...support of the components, from initial design & development, procurement and full characterization... 
    Permanent employment
    Internship
    Work from home
    Shift work

    Marvell

    Santa Clara, CA
    5 days ago
  • $126.7k - $158.4k

    Archer, based in Santa Clara, California, is seeking a Senior Manufacturing Design Engineer for Ground Support Equipment (GSE). This role is pivotal in ensuring that Archer's innovative eVTOL aircraft are fully supported post-manufacturing. You will collaborate with various... 

    Archer

    Santa Clara, CA
    2 days ago
  • Change the world. Love your job. The Emerging Packaging and Test Team at Texas Instruments is looking for a Magnetics and Passives Integration Technologist. As a member of our packaging team, you'll have the chance to interact with many product groups and functions. You... 
    Worldwide

    Texas Instruments

    Santa Clara, CA
    2 days ago
  •  ...intelligent symphony of technology and humans designing meaningful and sustainable experiences....  .... Job Title: System Design Test Engineer Location: Cupertino, CA Onsite/...  ...recruiters for more details on our Benefits package. The exact offer terms will depend on... 
    Contract work
    Remote work

    Yantran LLC

    Cupertino, CA
    4 days ago
  • $85k - $130k

     ...in a fast-paced, technology driven organization where our test designs impact products that are used by millions of people around the...  ...Check.Our design staff includes electrical, software, mechanical engineers, and project managers. Our systems are supported by staff... 
    Temporary work
    For contractors
    H1b
    Work at office
    Work visa

    Circuit Check

    Santa Clara, CA
    1 day ago
  •  ...JD: Job Overview: We are looking for a highly skilled Physical Design Engineer to work at block level and/or top level for high-performance ASICs, SoCs, and custom silicon chips with strong scripting skills. The ideal candidate will be responsible for various aspects... 

    Rezolve Ai

    Sunnyvale, CA
    1 day ago
  • A semiconductor design company in Sunnyvale seeks an experienced professional for Power Electronics package design. Responsibilities include interaction with Product Lines and assembly partners to enhance designs. The ideal candidate has over 10 years of experience in package... 

    Alpha & Omega Semiconductor

    Sunnyvale, CA
    4 days ago
  • $132k - $207k

     ...Are you a Mask Layout Design Engineer who is seeking an outstanding opportunity? We are looking for a Senior Mask Layout Design Engineer - someone who is excited to join a growing group of diverse individuals responsible for handling high-speed mixed-signal circuit designs... 
    Remote work

    NVIDIA

    Santa Clara, CA
    3 days ago
  • $160k - $180k

     ...Rail Design Engineer in Santa Clara to develop rail track designs using CAD and design/check the track components. MS Trans Eng and BS Rail Transp Eng needed. Knowledge of track design and construction and railway superstructure. $160,000 to $180,000 /year. Resume to hr... 

    PGH Wong Engineering

    Santa Clara, CA
    4 days ago
  •  ...Job Title: Silicon CAD (Power) Engineer IV Location: Role is ONSITE- US: Austin, TX or Sunnyvale, CA Duration: 12 Months About...  ...PnR) flows. Experience analyzing Intellectual Property (IP) design for power characteristics and building run-time estimation... 

    Spectraforce Technologies

    Sunnyvale, CA
    5 days ago
  •  ...Principal Substrate and Packaging Engineer Fully onsite in the San Francisco Bay Area Full time opportunity $400-500K total compensation...  .../experience level) Industry leader in semiconductor design focused on advanced IC packaging and high‑speed interconnect... 
    Full time

    Fidelis Companies

    Santa Clara, CA
    4 days ago
  •  ...limits of what’s considered feasible? As part of our Battery Engineering group, you’ll help craft creative battery solutions that deliver...  ...improved hardware elements into a single, integrated design. Join us, and you’ll help us innovate new battery technologies... 

    Apple

    Cupertino, CA
    2 days ago
  •  ...Job Title: Senior Physical Design Engineer (MULTIPLE OPENINGS) Salary Range : $216,091-218,000/ Year / 40HRS/WK Location: Cupertino, CA Job Duties: Perform physical design implementation activities at full-chip, block-level, and partition-level... 

    Neetha Consulting LLC

    Cupertino, CA
    4 days ago
  • $120k - $200k

     ...systems, including hardware and software, to train and run the largest ML workloads for AGI. MatX is seeking a Silicon Design‑For‑Test (DFT) engineer to join our team as we create best‑in‑class silicon for high‑performance and sustainable GenAI. The successful candidate... 
    Full time
    Work experience placement
    Local area
    Remote work
    Monday to Friday
    Flexible hours

    MatX

    Mountain View, CA
    4 days ago
  • $168k - $258.75k

     ...We are looking for a Senior PCB Design Layout Engineer join the Hardware Layout team. NVIDIA has continuously reinvented itself over two...  ...considerations. With competitive salaries and a generous benefits package, we are widely considered to be one of the technology world... 

    NVIDIA

    Santa Clara, CA
    3 days ago
  • Design Verification Engineer page is loaded## Design Verification Engineerlocations: US-CA-Mountain View, California (Google): US-TX-Austin-Texas (Comcast Austin Innovation Ctr)time type: Full timeposted on: Posted Todayjob requisition id: R233497# **Position:**Design... 
    Hourly pay
    Full time
    Work experience placement

    Arrow Electronics

    Mountain View, CA
    3 days ago
  •  ...in Santa Clara, California is looking for an experienced ASIC Design Engineer to join their Integrated Wireless Technology team. As a key...  ...silicon debug. This role offers a competitive salary and benefits package, reflecting Qualcomm's commitment to its employees. #J-18808-... 

    Qualcomm

    Santa Clara, CA
    4 days ago
  • Advanced Micro Devices is looking for a Principal CAD PCB Physical Design Engineer in Santa Clara, California. This senior-level role involves PCB physical design for high-speed and high-power products. The candidate should excel in cross-functional collaboration and possess... 

    Advanced Micro Devices

    Santa Clara, CA
    3 days ago
  • $168k - $264.5k

    NVIDIA Corporation is seeking a Senior Circuit Design Engineer specializing in power delivery to join their team in Santa Clara, California. This role requires a strong background in analog and mixed-signal circuit design, with a focus on power solutions. Ideal candidates... 

    NVIDIA Corporation

    Santa Clara, CA
    2 days ago
  • Qualcomm is looking for an experienced engineer in Santa Clara to oversee the design and verification of mixed-signal integrated circuits for Power Management...  ...industry tools. A competitive salary and benefits package, including bonuses and RSU grants, are offered alongside... 

    Qualcomm

    Santa Clara, CA
    4 days ago

Do you want to receive more vacancies?

Subscribe and receive similar vacancies to Packaging Design Engineer. Be the first to apply!