Design Engineer - Timing Methodology
$143.8k - $230kBroadcom
Please Note:1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account)2. If you already have a Candidate Account, please Sign-In before you apply.Job Description:Broadcom's Timing Sign-Off group in Central Engineering is looking for an energetic and self-driven professional to join our team. Our group’s mission is to provide advanced timing sign-off methodologies to Broadcom’s chip teams with the goal of achieving best in class solutions with high yield and fully optimized margins. The candidate will participate and take ownership in Advanced Timing Sign-off methodology development and modeling for SOC and 3D/2.5D IC design. This includes complex studies and analysis of new concepts leading to design, development and improvement of existing and new solutions. The candidate should have experience in methodology development with deep knowledge of advanced silicon technologies, production testability and yield. The candidate should have Tapeout experience in high volume / high yield complex SOCs at advanced technology nodes. The candidate will be working closely with other experts across the company in a fast paced project oriented agile environment. The candidate must have the ability to prioritize well, communicate clearly, proactively deliver practical and quality solutions on-time, work well with external and internal partners, and possess advanced IC design engineering skills. The candidate will be expected to work across multiple facets of projects and juggle multiple responsibilities at the same time.Responsibilities: Develop and deploy timing signoff methodologies for advanced technology nodes.Design and implement SOC, 3D/2.5D IC & multi-die signoff solutions.Participate & Lead in EDA flow development for Primetime, Tempus & Innovus.Qualifications:The minimum engineering experience required is typically a BS degree in EE/CS with 12+ years of industry experience, or an MS degree or Ph.D. degree in EE/CS with 10+ years of industry experience.Strong hands-on experience in Timing Signoff methodology development and ownership.Strong hands-on experience in SOC and 3D/2.5D IC timing signoff. Strong hands-on experience with statistical data analysis and modeling.Strong hands-on experience in silicon technologies, testability and yield. Strong hands-on experience with industry standard STA tools such as Primetime and Tempus.Strong hands-on experience developing scripts in TCL, Python, Perl, Unix shell and flow automation.Experience with revision control, issue management/defect tracking, continuous integration, and continuous delivery/deployment tools.Strong analytical skills and extremely detail oriented, organized and methodical.Strong communication skills. Clear and concise.Strong multitasking and context switching skills.Optimistic yet pragmatic attitude.Demonstrable skills for quick ramp-up.Ability to stay calm under extreme pressure. Team player.Able to work with minimum supervision, handle ambiguity and drive problem solving to resolution autonomously. Compensation and BenefitsThe annual base salary range for this position is USD 143,800.00 To USD 230,000.00As a valued member of our team, you'll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company's growth. All subject to relevant plan documents and award agreements.Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.SummaryLocation: USA-California-San Jose-1320 Ridder Park DriveType: Full time
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...full product development—from design to qualification to... ...world. Your Impact As an ASIC Engineer, you will play a critical role... ...with System Verilog and UVM methodology. Experience with scripting using... ...Cisco for defined periods of time.U.S. employees are eligible for...SuggestedFull timeTemporary workWork experience placementLocal areaFlexible hours$125.7k - $203.1k
...full product development—from design to qualification to... ...and optimize low-power design methodologies (clock gating, power gating,... ...power optimizations. Achieve timing closure, signal integrity, and... ...requirements.Job SummaryJob number: 2030409Profession: Product and EngineeringSuggestedFull timeTemporary workLocal areaFlexible hours$184.7k - $324.8k
...groundbreaking Apple product!Come help us design the next generation of... ...and unusually talented engineer. As a member of our dynamic group... ...to craft and implement methodologies with a high impact on upcoming... ...design flows in an effective and timely manner. You will verify...SuggestedRelocation$166.6k - $296k
...passion to join a world-class Digital Design Engineering group and take imaginative and revolutionary... ...opportunity for Standard Cell Design Methodology and Flow Engineers. In this highly... ...models to study the circuit trends in timing, power, and area, and to potentially...SuggestedRelocation$100k
...Tenstorrent is looking for a mid- to senior-level Physical Design Engineer with a strong background in static timing analysis (STA). In this role, you will help... ...while partnering with Design and DFT teams on methodology updates and closure requirements.Use Python, Perl,...Permanent employment$129.3k - $225.3k
...add something.DescriptionAs an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC design in terms of timing. Key responsibilities include timing sign... ...the ASIC design timing closure flow and methodology.2+ years of experience in writing ASIC...Relocation$184.7k - $324.8k
...recognized and innovative CPU design team; you will contribute to... ...in the physical design (PD) methodology and optimization space. With... ...CPU, CAD, and design teams to engineer new flows/algorithms to improve... ...in digital circuits, timing/power concepts, and logic designExperience...Relocation$184.7k - $324.8k
...will be responsible for all aspects of timing including working with the... ...timing closure.DescriptionAs the CPU Design Timing Engineer, you will be responsible for the timing... ...designsUnderstanding of physical design tools and methodology including logic synthesis, PnR,...Relocation$168k - $264.5k
We are now looking for a Senior CPU Design Methodology Engineer!The complexity of chip development has greatly increased over the years. We are now... ...protected by law.SummaryLocation: US, OR, Hillsboro; US, TX, Austin; US, AZ, Remote; US, CA, Santa ClaraType: Full timeFull timeRemote work$129.3k - $194.7k
...responsible for the physical implementation of design partition(s) (from netlist to tapeout)... ...and facilitate logic changes to improve timing.- Work with the Physical Design team,... ....- Create and maintain scripts and methodologies for analysis and runs.- Create documentation...Relocation$100k
...of all seniorities.Tenstorrent is looking for a Physical Design CPU Methodology Engineer who defines and drives the implementation methodology, automation... ...across RTL-to-GDS implementation and signoff, including timing closure, power optimization, SI, EM/IR, extraction, and...Permanent employmentRemote work$136k - $218.5k
...world.We are now looking for a motivated Senior Physical Design and Timing Engineer to join our dynamic and growing team. If you want to challenge... ...improvements, critical-path planning and crafting, or methodology/workflow improvements.Hands-on experience in block, sub-...Full time$168k - $264.5k
...impact on the world.We are looking for a physical design engineer to be a part of NVIDIA’s physical design (PD) methodology team driving innovation in PD across all of... ...also do it at scale, in the shortest possible time. Your work in physical design methodology directly...Full timeRemote work- ...Inabia-Software- seeks a diligent Design/SDC Engineer in San Jose, CA for an onsite contract role. The engineer will drive timing constraints across fullchip designs, collaborate... ...clocking diagrams, and promoting block-to-fullchip SDC methodologies. #J-18808-LjbffrContract work
$136k - $218.5k
...world.NVIDIA's Advanced Package Engineering team sits at the intersection of cutting-edge chip design and the physical reality of... ...of use.Develop flows/tools and methodologies to construct, analyze, and validate... ..., CA, Santa Clara; US, TX, Austin; US, CA, RemoteType: Full timeFull time$168k - $264.5k
...world.NVIDIA is looking for best-in-class Senior Physical Design Methodology Engineer(s) - PPA Improvement Technology Scaling to join our outstanding... ..., power and clock distribution, chip assembly and P&R, timing analysis and closure, power and noise analysis and back-...Full time$150.4k - $277.6k
...Technologies group, you’ll help design and manufacture our next-... ...developing flows, tools and methodologies for future Apple products! You... ...We are looking for passionate engineers to join our team. In this role... ...RC extraction, IR and static timing analysis (STA).- Working...Relocation$184.7k - $324.8k
...Technologies group, you’ll help design and manufacture our next-... ...developing flows, tools and methodologies for future Apple products! You... ...We are looking for passionate engineers to join our team. In this role... ...RC extraction, IR and static timing analysis (STA).- Working...Relocation$2,500 per month
...frontier intelligence. We co-design chips, racks, software, and manufacturing... ...and staffed by leading engineers, Etched is redefining the... .... As a Physical Design Methodology Engineer, you will architect... ...speeds, directly accelerating our time-to-market and enabling PPA gains...Full timeWork at officeRelocation package- ...Inabia Software & Consulting Inc. in San Jose, CA is seeking a Design/SDC Engineer to help close fullchip timing across multiple modes. The role focuses on SDC development, STA analysis, and collaboration with front-end and back-end teams to refine timing constraints for...Full time
$136k - $218.5k
...boundary where architecture, design, firmware, and silicon meet reality... ...are looking for a hardware engineer who builds the methods, test... .... This tooling reduces the time from observation to root-... ...infrastructure, characterization methodologies, and bring-up playbooks that...Full timeShift work$176.6k - $247.3k
...Acceleration team you’ll be responsible for the design and optimization of Hardware in our data... ...for block and full-chip level static timing analysis• Write, debug & validate timing... ...and teamwork with other physical design engineers as well as with the RTL/Arch. teamsBasic...Full timeLocal areaFlexible hours- ...Silicon One team at Cisco as an ASIC Design Verification Engineer, where you'll contribute to... ...functional areas. Define new verification methodologies to support advanced design... ...running Gate Level Simulations with timing annotation on netlists. Debug issues...
- ...Job Title : Physical Design Engineer Client: Arrow Electronics Experience Required: 5+... ...for your partitions in coordination with methodology owners. Partner with the design team... ..., encompassing synthesis, PnR, timing convergence and physical verification....H1b
$2,000 per month
...impossible with GPUs, like real-time video generation models and... ...and staffed by leading engineers, Etched is redefining the infrastructure... ...for exceptional Physical Design engineers to join our team.... ...~ Tools, flow, and design methodology from RTL synthesis to GDSII sign...Work at officeRelocation package- ...Physical Design Engineer - Location: San Jose OR Irvine, CA Our client develops specialized... ...The engineer will develop and refine methodologies aimed at achieving strong PPA results... ...power grid creation, place and route, timing analysis, noise analysis, physical verification...Full timeH1bVisa sponsorshipRelocation package
- ...contribute to advanced-node physical design for complex ASIC and SoC... ..., driving implementation, timing closure, signoff, and design... ...CAD, technology, and product engineering teams, you will help deliver... ...quality silicon while advancing methodology, automation, and data-driven...
- ...Design/SDC Engineer San Jose CA (Day-1 Onsite) Contract You are a diligent Design/SDC Engineer... ...skills and a deep understanding of timing constraints, including clock groups,... .... Helping develop efficient methodology to promote block level SDCs to fullchip...Contract workWork experience placement
$173.61k - $246k
...technical individual contributor in design and validation of the on-chip... ..., synthesis, APR and full timing closure as well as... ...Master’s degree in Electrical Engineering or related field.Position requires... ...language;2. Digital ASIC design methodology;3. Mixed-mode design and...Full timeLocal areaImmediate startOverseas
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