Principal Digital Design Engineer — High‑Speed SoC & PCIe Expert
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Astera Labs seeks a Principal Digital Design Engineer to lead front-end circuit design for high-performance network controllers, including RTL, synthesis, IP integration, and block-level verification.
You will bring 8+ years in SoC/silicon for Switch ASIC, Networking, Server or Storage, with strong PCIe/Ualink/Esun/Ethernet experience and familiarity with Synopsys or Cadence flows; UVM verification and DFT are valued. San Jose, CA preferred.
#J-18808-Ljbffr Jobleads-USVacancy posted 5 hours ago
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