Senior Performance Co-Design Engineer, TPU
$174k - $252kSenior Performance Co-Design Engineer, TPU Company: Google Location: Sunnyvale, CA, USA Mid Experience driving progress, solving problems, and mentoring more junior team members; deeper expertise and applied knowledge within relevant area. Minimum qualifications: Bachelor’s degree in Computer Science, Electrical Engineering, Computer Engineering, a related field, or equivalent practical experience. 5 years of experience in performance modeling/engineering, computer architecture, co-design, or systems engineering. Experience programming in C++ or Python. Preferred qualifications: Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture. Experience with hardware/software co-design problems, especially performance analysis and identification at the pre-silicon stage. Experience enabling and optimizing large-scale ML models (e.g., LLMs, large embedding models). Experience with ML infrastructure, profiling tools, or deep learning inference/serving optimizations. Familiarity with accelerator architectures. About the job Google Cloud’s mission is to make every business successful through AI by combining cutting-edge technology, infrastructure, and talent. AI/ML software engineers in Cloud bridge the gap between pioneering models and a massive product vehicle reaching billions. Our talent density and AI-powered tools drive rapid development, rooted in a culture of empowerment and a bias to action. In this role, you aren’t just building technology; you’re shaping the frontier of enterprise and driving the evolution of advanced models. The TPU Chip Architecture and Performance Co-design team is at the forefront of optimizing Google’s custom AI silicon for next-generation machine learning models. As a Senior Performance Co-Design Engineer, you will focus and conduct LLM Serving Studies. In this role, you will work on analyzing and optimizing the serving performance of emerging models and use cases on our custom hardware. You will also work closely with hardware architects to influence the evolution of Google’s custom ML accelerators. The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide. We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. Individual pay is determined by factors including job-related skills, experience, and relevant education or training. US: $174000 - $252000 (USD) + 15% bonus target + equity + benefits Learn more about benefits at Google. Responsibilities Conduct comprehensive serving performance studies on (current and emerging) LLMs (1P/3P models). Develop and maintain advanced simulation, profiling, and modeling tools to identify bottlenecks, understand key characteristics and project serving workload performance. Partner with model researchers, software and hardware teams to co-design architectural improvements tailored to Large Language Model (LLM) inference latency and throughput. Drive data-backed decisions that influence the roadmap for future TPU/Cloud Silicon architectures. Information collected and processed as part of your Google Careers profile, and any job applications you choose to submit is subject to Google's Applicant and Candidate Privacy Policy. Google is proud to be an equal opportunity and affirmative action employer. We are committed to building a workforce that is representative of the users we serve, creating a culture of belonging, and providing an equal employment opportunity regardless of race, creed, color, religion, gender, sexual orientation, gender identity/expression, national origin, disability, age, genetic information, veteran status, marital status, pregnancy or related condition (including breastfeeding), expecting or parents-to-be, criminal histories consistent with legal requirements, or any other basis protected by law. See also Google's EEO Policy, Know your rights: workplace discrimination is illegal, Belonging at Google, and How we hire. If you have a need that requires accommodation, please let us know by completing our Accommodations for Applicants form. Google is a global company and, in order to facilitate efficient collaboration and communication globally, English proficiency is a requirement for all roles unless stated otherwise in the job posting. Equity is granted exclusively and discretionarily by Alphabet Inc. on the basis of an agreement concluded between you and Alphabet Inc. Alphabet Inc. is your sole contractual partner with respect to equity grants. GSU grants are not guaranteed, are discretionary, are subject to approval by the Alphabet Inc. board of directors or its delegate, the terms of the relevant Alphabet Inc. stock plan, and your grant agreement. They have no impact on statutory payments. Current or past grants do not confer an acquired right. #J-18808-Ljbffr Google
$174k - $252k
...comprehensive serving performance studies on (current and... ...and hardware teams to co-design architectural... ...the roadmap for future TPU/Cloud Silicon architectures... ...Computer Science, Electrical Engineering, Computer Engineering,... ...learning models.As a Senior Performance Co-Design...SeniorPerformanceWorldwide- Google Cloud is seeking a Senior Performance Co-Design Engineer for TPU work in Sunnyvale to optimize serving performance of large language models on custom AI silicon. You will analyze current and emerging models, build tools to probe bottlenecks, and influence architecture...SeniorPerformance
- ...edge technology, infrastructure, and talent. The TPU Chip Architecture and Performance Co-design team optimizes Google's custom AI silicon for... ..., including LLMs, on our own hardware. As a Senior Performance Co-design Engineer, you will focus on LLM Serving Studies, analyzing...SeniorPerformance
- Google Cloud’s TPU Chip Architecture and Performance Co-design team seeks a Senior Performance Co-Design Engineer to drive LLM serving studies and optimize serving performance on our custom AI silicon. You’ll partner with researchers and hardware teams to balance latency...SeniorPerformance
- Google Sunnyvale is seeking a Senior Performance Co-design Engineer for LLM training to shape future ML accelerators and ensure efficient training across... ..., build modeling infrastructure and tooling, and influence the roadmap for TPU/Cloud Silicon #J-18808-Ljbffr GoogleSeniorPerformance
- Google Cloud’s TPU Chip Architecture and Performance Co-design team seeks a Senior Performance Engineer in Sunnyvale to optimize AI silicon for large language model training. You will study training workloads for 1P and 3P models, shaping hardware and software architectures...SeniorPerformance
$174k - $252k
Senior Performance Co-design Engineer, LLM Training Google, Sunnyvale, CA, USA Mid Experience driving progress, solving problems, and mentoring more junior... ...and driving the evolution of advanced models. The TPU Chip Architecture and Performance Co-design team is at the...SeniorPerformanceWorldwide- Google Cloud in Sunnyvale, CA seeks a Senior TPU Co-Design Engineer to shape AI/ML hardware acceleration and drive TPU architecture across training and inference. You will bridge research, software, and hardware teams to maximize scalability, quality, and efficiency of...Senior
- Google is seeking a Staff Co-Design Engineer to shape the TPU architecture and accelerate AI/ML hardware. You will drive silicon solutions powering... ...work across AI research and engineering to push the performance and efficiency of TPU-based systems. As part of the TPU...Performance
- Google Cloud TPU is seeking a Co-Design Engineer in Sunnyvale, CA to shape AI/ML hardware acceleration. You’ll drive TPU architecture, bridging ML research and hardware design, and contribute to performance-focused silicon solutions powering Google’s AI workloads. You’ll...Performance
- Google is seeking a Staff Co-Design Engineer to shape AI/ML hardware acceleration with TPU architecture integration. You’ll help drive next-generation silicon solutions... ...hardware and ML research teams to deliver high-performance accelerators. You will bridge model architecture...Performance
$192k - $278k
...software stack to enable performant training and serving of... ...across hardware design, compiler development,... ...s degree in Electrical Engineering, Computer Engineering,... ..., or hardware-software co-design.Experience developing... ...to drive cutting-edge TPU (Tensor Processing Unit...PerformanceWorldwide$168k - $264.5k
...spec to final shipment. NVIDIA's Silicon Co-Design Group sits at the convergence of architecture... ...consequences: escapes, yield loss, and performance loss.We're hiring a Senior Manufacturing & System Co-Design Workflow Engineer to lead the methodology and infrastructure...SeniorPerformanceFull timeImmediate start$163k - $237k
...microarchitecture and RTL execution to deliver high-performance network design components which meet strict power,... ...:Bachelor's degree in Electrical Engineering, Computer Engineering, Computer... ...an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology...SeniorPerformanceWorldwide- Google Sunnyvale is seeking a Senior Performance Co-design Engineer focused on LLM training to drive the hardware-software co-design for next-gen ML accelerators. You will lead modeling, analyze bottlenecks, and partner with ML researchers to optimize training workloads...SeniorPerformance
- ...is shaping the future of AI/ML hardware acceleration with TPU architecture, delivering high-performance, power-efficient accelerators for training and serving massive ML models. As Senior Staff Co-Design Engineer, you will bridge model architecture innovation and...SeniorPerformance
$240k - $334k
TPU Co-Design Engineer, Google Cloud Google Sunnyvale, CA, USA Advanced Experience owning outcomes... ...design. Experience developing systems for performance modeling, simulation, or system... ...integration within AI/ML-driven systems. As a Senior Staff Co-Design Engineer on the TPU...PerformanceWorldwideShift work$163k - $236k
...document the microarchitecture for digital designs within the TPU.Partner with Verification to develop... ...of internal design tools, flows, and engineering methodologies.Minimum qualifications:... ...design.Experience in optimizing for performance, power, and area.Cross-functional...SeniorPerformanceWorldwide$163k - $236k
...Drive RTL development, debug functional/performance simulations.Meet schedule commitments... ...qualifications:Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science... ....8 years of experience with RTL design using Verilog/System Verilog and microarchitecture...SeniorPerformanceWorldwide$163k - $236k
...management and control subsystem's design microarchitecture... ...Bachelor's degree in Electrical Engineering, Computer Engineering, Computer... ...opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology... ...require you to coordinate and co-design with our software and...SeniorWorldwide$138k - $198k
Design Technology Co-Optimization Engineer Sunnyvale, CA, USA Qualifications Bachelor's degree in Electrical Engineering... ...-class IP blocks, such as high-performance CPU/GPU cores, SRAM arrays, or high... ...acceleration, drive cutting‑edge TPU technology that powers Google’s...PerformanceWorldwide$136k - $218.5k
...group delivers innovative PHY designs that power the most powerful... ...channels, supporting NVIDIA's high-performance interconnect protocols:... ...networking and enabling the era of Co-Packaged Optics (CPO) for... ...or M.S. degree in Electrical Engineering or equivalent experience.5+...SeniorPerformanceFull time$163k - $237k
Participate in the Physical Design of complex blocks.Contribute to... ...to achieve the best Power/Performance Analysis (PPA). This includes... ...Bachelor's degree in Electrical Engineering, Computer Engineering,... ...opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology...SeniorPerformanceWorldwide$136k - $218.5k
The SCG Architecture team is hiring a Senior Power Integrity Co-Design Engineer to architect and deliver di/dt mitigation across silicon, package, board, and platform. This role bridges architecture, silicon, and platform — translating product noise targets into shipped...SeniorFull timeLive in$163k - $236k
...microarchitecture and RTL development, ensuring high-performance designs that strictly adhere to Power,... ...:Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science... ...have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology...PerformanceWorldwide$138k - $197k
...complex microarchitecture for the TPU, writing high-quality, performant, and power-efficient RTL code primarily... ...continuous enhancement of internal design tools, flows, and methodologies.... ...qualifications:Bachelor's degree in Electrical Engineering, Computer Engineering, Computer...PerformanceWorldwide$163k - $236k
...from HLS code to generated RTL.Design and maintain advanced... ...specific methods such as C/RTL co-simulation, formal equivalence... ...verifiability and mentor junior engineers on the nuances of HLS verification... ..., delivering unparalleled performance, efficiency, and integration....SeniorPerformanceWorldwide$136k - $218.5k
NVIDIA is seeking a hardworking Senior ASIC Design Verification Engineer to help drive sign-off strategies for... ...outstanding opportunity to influence performance of the next generation GPU and SoC,... ...knowledge or work experience in co-simulation environments such as VCS...SeniorPerformanceFull timeWork experience placementRemote work$164.47k - $311.89k
...Description: About the RoleIntel is seeking a Senior Design Verification Engineer for the Silicon Chassis team. In... ...signoffs and achievement of performance and power metricsLead IP delivery to... ...methodologies including UVM, SVA, ABV, and co-simulation; proficiency in low-power...SeniorPerformanceFull timeInternshipLocal areaImmediate startShift work- Google Cloud's TPU Chip Architecture and Performance team analyzes ML workloads to balance performance and cost... ..., compiler developers, and systems engineers to drive architecture decisions and... ...analysis, hardware/software co-design, and scalable estimation methods for...SeniorPerformance
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