Sr ASIC Design Verification Engineer (NetSec)

Job Summary As a Design Verification engineer on the ASIC team, you will ensure that the ASICs in our groundbreaking next‑generation firewall products meet or exceed industry‑leading requirements for features, performance, and reliability. You will define verification methodologies, architect test benches, write test plans, specify coverage, write tests, and debug. You will work on diverse platforms including simulation, emulation, formal verification, and silicon validation. Your Impact Collaborate with engineers in software, architecture, design, and verification teams to create comprehensive pre‑silicon verification plans across simulation, emulation, and formal verification Plan and execute simulation test plans using sophisticated coverage‑driven, constrained‑random methodologies Develop flows, methodologies, and infrastructure for emulation Run and debug emulation tests in close collaboration with system architects, software engineers, and ASIC designers Define new tools and methodologies to continuously improve quality and velocity Create powerful programs in Python to automate triage, coverage closure, and metrics‑driven verification Qualifications Your Experience BS in EE, CE, or CS required or equivalent military experience – MSEE preferred Minimum 5 years experience in ASIC design verification Demonstrated success in taking multiple ASIC products from concept to mass production Expertise in SystemVerilog, UVM, defining test plans (including adversarial testing), developing rich functional coverage models, creating scalable test benches, implementing self‑checking, reusable constrained‑random tests, debugging failures, closing coverage. Preferred experience: Networking and cybersecurity, formal property verification, silicon validation (bring‑up, test, debug, regression), modeling in Python and C/C++, driver code in C, scripting (Python, Perl, Unix shell) to automate verification tasks. Demonstrated ownership and independence in planning, debugging complex failures, closing metrics‑driven tasks, driving vendors, reporting status. Strong leadership, collaboration, communication skills. Compensation Disclosure The compensation offered for this position will depend on qualifications, experience, and work location. For candidates who receive an offer at the posted level, the starting base salary (for non‑sales roles) or base salary + commission target (for sales/commissioned roles) is expected to be the annual range listed below. The offered compensation may also include restricted stock units and a bonus. A description of our employee benefits may be found here. Immigration Sponsorship Is role eligible for Immigration Sponsorship? No. We will not sponsor applicants for work visas for this position. Equal Opportunity and Accommodation We’re committed to providing reasonable accommodations for all qualified individuals with a disability. Please contact us at View email address on click.appcast.io if you require assistance. Palo Alto Networks is an equal opportunity employer. We celebrate diversity in our workplace, and all qualified applicants will receive consideration for employment without regard to age, ancestry, color, family or medical care leave, gender identity or expression, genetic information, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran status, race, religion, sex (including pregnancy), sexual orientation, or other legally protected characteristics. All your information will be kept confidential according to EEO guidelines. #J-18808-Ljbffr