Senior ASIC Physical Design Lead: Sub-7nm Timing & Flows
Hader Solutions
Hader Solutions in Austin, TX seeks a Senior ASIC Physical Design Engineer to lead physical implementation of assigned SoC partitions, driving synthesis, place-and-route, and static timing closure. You will work on-site with design, DFT, and architecture teams to resolve implementation and signoff issues. You will manage EM/IR analysis, PDN planning and verification, oversee LEC and physical verification signoff, and collaborate with EDA vendors to debug and improve flows. #J-18808-Ljbffr Hader Solutions
Vacancy posted 1 day ago
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