RTL Design Engineer

Founding RTL Design Engineer / Member of Technical Staff Acceler8 Talent is partnering with an early-stage startup to hire an RTL Design Engineer to join as an MTS. They’re building advanced AI-driven tools and infrastructure for custom ASIC development at scale, focusing on enabling next-generation domain-specific hardware architectures for modern machine learning workloads. Their team combines expertise across AI systems, compilers, and silicon design to develop tightly integrated hardware/software solutions for emerging compute platforms. We are seeking experienced RTL Design Engineers to drive the microarchitecture and RTL implementation of critical SoC blocks and subsystems targeting production silicon. This role involves defining, driving, and refining block-level microarchitecture specifications for core hardware accelerator components. What You’ll Do Own AI-assisted RTL design flows end-to-end at the frontend level, including code generation and incorporation of feedback from lint, CDC, synthesis, and timing closure flows Collaborate closely with architecture teams to refine microarchitectural specifications, resolve implementation trade-offs, and feed timing, power, and area insights back into architectural decisions and internal tooling flows Define and maintain interface specifications for block- and subsystem-level integration, including standard and custom protocols such as AXI and AXI-Stream Build and maintain RTL infrastructure including automation scripts, regression flows, lint/CDC waivers, and integration collateral Work closely with verification teams to support bring-up through reference models, assertions, test plans, and architectural documentation Collaborate with software and ML teams to improve internal AI-assisted hardware development workflows based on practical implementation experience Support FPGA prototyping efforts for early functional validation What We’re Looking For Qualifications & Skills Bachelor’s, Master’s, or PhD in Electrical Engineering, Computer Engineering, or a related field 5+ years of RTL design experience, including at least one advanced-node tapeout Experience designing specialized hardware accelerators or SoCs/IPs integrating AI/ML, GPU, DSP, vector, or related accelerator technologies Strong SystemVerilog RTL development skills with emphasis on synthesizable, lint-clean, parameterized, modular, and reusable designs Hands-on experience designing compute datapaths and data movement infrastructure such as MAC arrays, vector units, accumulators, SRAM controllers, arbiters, DMA engines, and scratchpad memory systems Strong understanding of SoC implementation methodology including synthesis, timing constraints, CDC analysis, reset strategies, AMBA protocols (AXI/AHB/APB), and power management techniques Strong Python skills for design automation, regression infrastructure, and tooling development Experience owning power, performance, and area (PPA) closure from RTL through synthesis while collaborating with physical design teams Ability to lead RTL design efforts and grow into technical leadership responsibilities over time Preferred / Bonus Experience Low-power design techniques including clock gating, power gating, multi-voltage domains, and UPF methodologies FPGA prototyping experience, particularly with Xilinx toolchains Familiarity with SIMD/VLIW execution pipelines and instruction-driven datapath architectures Experience writing SVA assertions and functional coverage for design-side verification Prior ownership of reusable IP delivery such as DMA controllers, memory subsystems, interconnects, or related SoC infrastructure blocks Track record of developing energy-efficient, high-performance accelerator technologies and related research or product development efforts #J-18808-Ljbffr