Senior RTL Design Engineer - SoC & IP Subsystems
$100k - $180kWipro
Wipro is seeking a Digital Design Engineer located in Mountain View, California, with 8-10 years of experience in VLSI Physical Place and Route. Key responsibilities include architecture development for System on a Chip subsystems and RTL integration. The role requires knowledge of System Verilog and power design principles. Compensation ranges from $100,000 to $180,000, depending on skills and experience, with standard benefits offered. #J-18808-Ljbffr Wipro
Vacancy posted 3 hours ago
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