Staff SOC Physical Design Engineer

Company Qualcomm Technologies, Inc. Job Area Engineering Group, Engineering Group > ASICS Engineering General Summary This individual leads, plans, synthesizes ambiguous or conflicting requirements and performs the complex responsibility of the Physical Design Flow of high-speed DDR, graphics, physical verification flows, micro‑architecture, SOC algorithm design and modeling, and methodology, focusing on target power utilization and optimization for system‑on‑chip (SoC) products and how these features impact power and performance. Responsibilities Floor Planning, Clock Tree Synthesis, Place and Route, PDN, Timing analysis and closure. Perform various physical verification checks (such as LVS, DRC, design‑for‑manufacturing & design‑for‑yield) at the chip and block levels. Provide schedules and support cross‑functional engineering effort to drive to signoff closure for tapeout. Act as a strong contributor at design reviews and project meetings, communicating and implementing a development plan. Qualifications Master's Degree (or foreign academic equivalent) in Electrical Engineering, Computer Engineering, Computer Science or related field and three (3) years of experience in a related occupation. Bachelor's Degree (or foreign academic equivalent) in Electrical Engineering, Computer Engineering, Computer Science or related field and seven (7) years of progressive experience in a related occupation. Employer will accept any suitable combination of education, training or experience. Pay Range $154,742.00 - $210,00.00/year EEO Employer Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification. #J-18808-Ljbffr Qualcomm