Sr. Staff Engineer, ASIC Design

Location: San Jose (on-site)

Ayar Labs is shattering AI data bottlenecks by moving data at the speed of light. As pioneers of co-packaged optics (CPO), we are using light instead of electricity to move data faster, further, and with a fraction of the energy needed to fuel the explosive growth of AI models. Backed by industry giants like NVIDIA, AMD and Intel and manufactured in partnership with the world's leading semiconductor ecosystem, Ayar Labs' co-packaged optics solution is key to unleashing next-generation AI scale-up architectures.

The ASIC Sr. Staff Engineer is responsible for the design, bring-up, and debug of complex digital subsystems within an electro-optical digital SoC. You will work in a dynamic startup environment as part of a small IC design team, with each team member expected to contribute across a broad range of tasks while gaining new skill sets to grow with the company.

The ideal candidate is a hands-on self-starter who can craft specifications based on input from colleagues, customers, and industry and who can effectively manage his or her own time to take projects to completion with limited supervision and guidance.

Key Responsibilities

Develop detailed digital algorithm specifications in collaboration with analog, photonics, and firmware engineers

Develop and optimize RTL in verilog for use in complex electro-optical ASICs

Develop models and testbenches for digital and mixed-signal blocks

Create clear documentation of their designs to enable backend ASIC engineers to perform physical implementation (clocks and timing constraints, floorplan guidance, testability) and collaborate to ensure timing signoff

Bringup, evaluation, and debug of in-house custom silicon using python scripting, firmware, and control systems

Contribute to automated design methodologies and flows for ASIC digital design

Hands-on work with high-speed interconnects and optical systems

Required Qualifications

BS in Electrical Engineering, Computer Engineering, or related fields

5+ years of work or academic experience in ASIC design

History of assuming responsibility for a variety of technical tasks and completing projects independently

Mastery of Verilog and SystemVerilog for both RTL design and verification

Proficient in ASIC verification (XCelium, VCS, Questa) tools

Proficient in low-level programming languages (C, C++)

Proficient in Python

Working knowledge of digital timing constraints and ASIC tool flows

Experience working on digital designs with multiple clock domains and clock dividers

Experience with SOC interconnect fabrics (AMBA AXI/AHB/APB)

Preferred Qualifications

MS in Electrical Engineering, Computer Engineering, or related fields

Proficient in ASIC synthesis (Genus, Design Compiler) tools

Proficient in writing timing constraints and deep understanding of timing analysis

Working knowledge integrating custom blocks in a digital-top flow (LEF, lib, etc.)

Performed silicon bring-up, debug, and evaluation

Working knowledge of FPGAs and/or microcontroller platforms

Working knowledge of the Cadence Virtuoso design environment, schematic entry, layout, and simulation

Experience with DFT methodologies and flows such as scan insertion, BIST, ATPG, etc

Knowledge of high-speed SerDes or SerDes components

Some knowledge of optics and control systems

Salary Range: $180,000 - $223,000

Ayar Labs is an Equal Opportunity Employer and is strongly committed to all policies which will afford equal opportunity employment to all qualified persons without regard to age, sex, national origin, race, color, ethnicity, creed, religion, gender identity, sexual orientation, disability, veteran status, or any other characteristic protected by law. It is the policy of Ayar Labs to provide reasonable accommodation when requested by a qualified applicant or employee with a disability, unless such accommodation would cause an undue hardship. Veterans are more than welcome and encouraged to apply.

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