CPU Custom Circuit Lead

THE ROLE

As a Custom Design Lead, you will participate in and direct work in the following :

• Lead a small team of engineers responsible for development of custom memories (SRAM and register files) used in development of a high performance CPU

• Manage and help participate in schematic development and characterization of custom memories (SRAM, register files) to optimize PPA at advanced process nodes.

• Supervise layout implementation, defining macro floor planning, critical routing specifications, and driving physical design verification (PDV) closure.

• Manage engineers performing end-to-end memory IP signoff: schematic and layout through DRC/LVS/antenna, parasitic extraction, and characterization (timing, power, and noise in Liberty/CCS format) across PVT corners, meeting target PPA commitments.

• Partner with Foundry/PDK, CAD, Physical Design, RTL and DFT teams to benchmark new process technology, validate IP on testchips, and co-optimize custom memories for downstream design PPA.

• Collaborate closely with RTL, providing explicit custom memory functional specifications, timing behaviors, and state definitions to support accurate RTL modeling.

• Define and drive adoption of Tools, Flows, and Methodology (TFM) — including characterization automation and compiler QA — to raise design efficiency and set team-wide best practices.

MINIMUM QUALIFICATIONS

• Deep knowledge in memory arrays — bit cells, sense amps, decoders — in advanced CMOS nodes.

• Deep knowledge of SPICE simulations, SRAMs / Register File circuit margins, and special memory cells architecture.

• Proficient with industry-standard EDA tools for schematic, layout, extraction, and characterization, applied to custom memory design workflows.

• Demonstrated track record delivering production-level custom memory IP through tape-out, with silicon-validated PPA in high-volume products.

• Deep understanding of end-to-end signoff for custom memories — DRC/LVS/antenna, extraction, Spice margins, STA, EM/IR — and characterization flows spanning timing, power, and noise.

• Well-versed in STA and Liberty/CCS lib model development and correlation, including timing and power characterization for both Functional and DFT (Design for Test) modes.

• Strong communication and collaboration skills, comfortable working directly with foundry, CAD, and physical design partner teams.

REQUIREMENTS — PREFERRED

• Experience managing engineers and providing technical leadership to a custom circuit team

• Substantial experience across the full embedded memory design flow — architecture, circuit design, physical implementation, compiler automation, characterization, and timing/model generation.

• Experience designing and optimizing complex memory sub-blocks (self timed design tracking loops, read/write assist schemes, power-gating headers) and translating PDK device characteristics into cell/bit-cell circuit decisions.

• Proven PPA-focused execution, including SRAM architecture trade-offs, critical-path modeling, full-cut analysis, and extensive Monte Carlo variation studies.

• Demonstrated experience converging on macro verification, including functional formal equivalence (LEC) and dynamic SPICE-versus-RTL co-simulation (cosim) methods.

• Experience partnering directly with foundries on PDK bring-up and device co-optimization (DTCO) at leading-edge nodes.

• Proficient in Python, Perl, or TCL to build and improve design, characterization, and QA automation.

• Experience using Agentic AI tools for productivity and automation.

$200,000 - $300,000 a year