Physical Design Engineer

At SK hynix memory solutions, we're at the forefront of semiconductor innovation, developing advanced memory solutions that power everything from smartphones to data centers. As a global leader in NAND flash technology and memory solutions, we drive the evolution of advancing mobile technology, empowering cloud computing, and pioneering future technologies. Our cutting‑edge memory technologies are essential in today's most advanced electronic devices and IT infrastructure, enabling enhanced performance and user experiences across the digital landscape.

We're looking for innovative minds to join our mission of shaping the future of technology. At SK hynix memory solutions, you will be part of a team that's pioneering breakthrough memory solutions while maintaining a strong commitment to sustainability. We're not just adapting to technological change – we're driving it, with significant investments in artificial intelligence, machine learning, and eco‑friendly solutions and operational practices. As we continue to expand our market presence and push the boundaries of what's possible in semiconductor technology, we invite you to be part of our journey to creating the next generation of memory solutions that will define the future of computing.

About the Role

Join our Physical Design (SoC Integration) team responsible for delivering high-performance SoC designs from RTL to GDS. As a Sr. Staff Physical Design Engineer, you will lead physical implementation efforts for advanced-node designs, driving critical blocks through synthesis, placement, CTS, routing, and signoff. You will work closely with front-end, DFT, power, and analog teams to optimize PPA (Power, Performance, Area) while ensuring silicon success. This role requires deep hands‑on expertise across the full physical design flow as well as leadership to mentor junior engineers and define methodologies for the team.

Responsibilities

• Lead physical design implementation from synthesis through GDS for high-performance blocks or full-chip SoC designs in advanced process nodes (7nm, 5nm, 3nm)
• Execute and optimize synthesis, placement, clock tree synthesis (CTS), and routing using industry-standard P&R tools (Synopsys ICC2/Fusion Compiler or Cadence Innovus)
• Drive timing closure and signoff using PrimeTime (PT), including advanced analysis such as SI, AOCV/POCV, crosstalk, and ECO implementation
• Perform RC extraction using StarRC or Quantus and ensure strong correlation between extraction and STA results
• Own physical verification signoff with Mentor/Siemens Calibre, resolving DRC, LVS, ERC, and antenna violations in complex FinFET layouts
• Conduct power integrity analysis using Ansys RedHawk(Redhawk-SC), including static/dynamic IR drop and EM analysis; implement power grid and decap optimizations
• Develop and maintain physical design flows and automation scripts (Tcl, Perl, Python), mentor junior engineers, and collaborate with cross-functional teams to achieve tapeout schedules

Minimum Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, or related field (Master's preferred)
• 6+ years of hands‑on experience in ASIC physical design with proven tapeout success
• Expert-level proficiency in synthesis, placement, CTS, and routing using Synopsys or Cadence P&R tools
• Deep knowledge of static timing analysis (STA) and PrimeTime signoff, including multi‑corner/multi‑mode closure
• Demonstrated experience with physical verification using Calibre (DRC, LVS, ERC) and IR drop/EM analysis using RedHawk

Preferred Qualifications

• Experience at 5nm or 3nm process nodes with FinFET and multi-patterning design rules
• Familiarity with low-power design techniques including UPF, clock gating, multi‑Vt, and voltage islands
• Strong programming skills in Tcl, Perl, and Python for flow automation and data analysis
• Knowledge of ECO implementation and clock reconstruction (CRPR, useful skew) methodologies
• Experience leading or mentoring a team of physical design engineers on complex SoC projects
• Exposure to memory-centric interfaces and systems such as SSD SoC, HBM, or HBF (High Bandwidth Flash) base die designs (a plus, not required)
• Familiarity with chiplet and die‑to‑die (D2D) interconnect technologies, including Universal Chiplet Interconnect Express (UCIe) or equivalent D2D PHY protocols (a plus, not required)

BASE COMPENSATION: $160,000/yr - $220,000/yr

REGARDING COMPENSATION:

SK hynix memory solutions America Inc. offers you the opportunity to apply your skills to exciting projects while working with innovative teams. Our compensation package is complimented by a generous benefits package including medical, dental, vision, life insurance and a company 401(k) match, as well as cafeteria, onsite gym and much more. If you are motivated by technical challenges, we offer a collaborative work environment that encourages career growth.

The salary offered to a selected candidate will be tailored based on several factors, including the location, job grade, relevant knowledge, skills, and experience. We also take into account the internal equity among our current team members to ensure fairness and competitiveness.

This role requires you to work onsite 5 days a week at our San Jose location.

If you are not located in San Jose, CA are you willing to relocate?

Voluntary Self-Identification

For government reporting purposes, we ask candidates to respond to the below self-identification survey.Completion of the form is entirely voluntary. Whatever your decision, it will not be considered in the hiringprocess or thereafter. Any information that you do provide will be recorded and maintained in aconfidential file.

As set forth in SK hynix memory solutions America Inc.’s Equal Employment Opportunity policy,we do not discriminate on the basis of any protected group status under any applicable law.

If you believe you belong to any of the categories of protected veterans listed below, please indicate by making the appropriate selection.As a government contractor subject to the Vietnam Era Veterans Readjustment Assistance Act (VEVRAA), we request this information in order to measurethe effectiveness of the outreach and positive recruitment efforts we undertake pursuant to VEVRAA. Classification of protected categoriesis as follows:

A "disabled veteran" is one of the following: a veteran of the U.S. military, ground, naval or air service who is entitled to compensation (or who but for the receipt of military retired pay would be entitled to compensation) under laws administered by the Secretary of Veterans Affairs; or a person who was discharged or released from active duty because of a service-connected disability.

A "recently separated veteran" means any veteran during the three-year period beginning on the date of such veteran's discharge or release from active duty in the U.S. military, ground, naval, or air service.

An "active duty wartime or campaign badge veteran" means a veteran who served on active duty in the U.S. military, ground, naval or air service during a war, or in a campaign or expedition for which a campaign badge has been authorized under the laws administered by the Department of Defense.

An "Armed forces service medal veteran" means a veteran who, while serving on active duty in the U.S. military, ground, naval or air service, participated in a United States military operation for which an Armed Forces service medal was awarded pursuant to Executive Order 12985.

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