Video ASIC Design Intern — RTL/HLS & Silicon IP
LPU Batangas
LPU Batangas is seeking an undergraduate intern to design hardware accelerators for video encoding and processing as part of the Video Silicon IP team. You will collaborate with architecture, algorithm, and verification groups to build high-performance, low-power ASIC IPs. The role requires knowledge of video codecs, RTL design with SystemVerilog or HLS, UVM/SystemC/DPI, and strong Python scripting for automation. Day one benefits apply to interns where eligible. #J-18808-Ljbffr LPU Batangas
Vacancy posted 1 day ago
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