SoC Power Architecture Engineer - Processor Subsystem

We are seeking an experienced SoC Power Architecture Engineer to define, design, and implement power domain architectures for ASIC‑based processor subsystems targeting satellite IoT connectivity applications. This role focuses on partitioning and structuring power domains within complex processor subsystems, with a strong emphasis on aggressive duty cycling, ultra‑low standby power, and constrained energy budgets inherent to satellite IoT end‑node devices. Key Responsibilities: Define and architect power domains within processor subsystems, including always‑on, switchable, and retention domains optimized for low‑power use cases. Design and implement power domain partitioning strategies for subsystems involving embedded processors, bus interconnects, and associated peripherals. Develop and integrate supporting logic for power domain separation, including power switches, isolation cells, level shifters, and retention registers. Define and implement power control sequencing and state machines for domain power‑up/power‑down flows, with emphasis on fast wake‑up latency requirements for satellite link windows. Collaborate with SoC architects, physical design, and verification teams to ensure power domain intent is correctly captured in UPF. Drive definition of low‑power modes (e.g., Sleep, Deep Sleep, Power‑Off) and their interaction with system‑level power management in battery‑ or energy‑harvesting‑powered IoT devices. Work with processor subsystem reference designs as a baseline and adapt the power architecture to the unique demands of satellite IoT SoCs. Support power‑aware synthesis, place‑and‑route, and sign‑off flows in coordination with the physical design team. Define and review power intent files (UPF/IEEE 1801) and ensure consistency with RTL implementation. Engage with verification teams to ensure power domain structures are properly tested and validated across all low‑power operating modes. Required Qualifications: Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field. 7+ years of experience in ASIC/SoC design with a strong focus on low‑power architecture. Deep hands‑on experience with power domain definition, isolation strategies, and retention architectures. Proficiency with UPF (IEEE 1801) power intent format. Strong knowledge of RTL design using SystemVerilog or VHDL. Demonstrated experience optimizing for ultra‑low power consumption in energy‑constrained applications such as IoT, wearables, or similar. Familiarity with low‑power synthesis and physical design constraints. Preferred Qualifications: Experience with Arm Corstone or similar processor subsystem IP, including Arm processor subsystems (Cortex‑M series) or similar embedded processor architectures. Knowledge of AMBA bus protocols (AHB, APB, AXI) as they relate to power domain crossings. Experience with power analysis tools (e.g., Synopsys PrimeTime PX, Cadence Joules). Understanding of battery‑powered and energy‑harvesting device constraints as they influence SoC power architecture decisions. Familiarity with power management ICs (PMICs) and their interface to domain control logic. This is a full‑time, exempt position based out of our Saratoga office. The target base pay for this position is $150,000 – $220,000 annually. The total compensation package will be determined by various factors, such as relevant job‑related knowledge, skills, and experience. We do not currently provide employment sponsorship for candidates who do not hold work authorization for the location of this role. Benefits: An opportunity to really make a difference. Sustainability at our core. Fair and honest workplace. Innovative thinking is encouraged. Competitive salaries. Continuous learning and development. Health and wellness care options. Financial solutions for the future. Optional legal services (US only). Paid holidays. Paid time off. #J-18808-Ljbffr E-Space