Senior STA & Synthesis Engineer for Low-Power WiFi SoCs
Nutanix
Qualcomm Atheros, Inc. in California, Santa Clara, is seeking an experienced Static Timing Analysis and Synthesis Engineer to drive timing closure for Wi‑Fi SoCs and sub-systems. You will collaborate with RTL, DV, DFT and PD teams to deliver high‑quality silicon on aggressive schedules. The role emphasizes pre- and post-layout STA, MMMC timing, low‑power checks, and ECO-driven improvements using PrimeTime and Synopsys tools, with a focus on PPA balance and robust sign‑off. #J-18808-Ljbffr Nutanix
Vacancy posted 1 day ago
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