Design Verification Lead — PCIe/CXL & High‑Speed IP
Advanced Micro Devices
Advanced Micro Devices (AMD) seeks a Design Verification Engineer Lead in the AECG Group based in San Jose, CA. You will lead front-end design and integration efforts for FPGA/ASIC IP verification and first-pass silicon success for PCIe and CXL-based solutions. You will collaborate across architecture, IP design, physical design, firmware and product engineering, shaping verification strategies, developing UVM environments, and mentoring distributed teams. #J-18808-Ljbffr Advanced Micro Devices
Vacancy posted 3 days ago
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