Static Timing Analysis Manager, Full Chip, SOC, Implementation

About the job Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google’s direct‑to‑consumer products. You’ll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google’s mission is to organize the world’s information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people’s lives better through technology. US: $192,000 – $279,000 (USD) + 20% bonus target + bonus + equity + benefits. Minimum Qualifications Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 10 years of experience with silicon implementation and chip integration. Experience with STA sign‑off constraint authoring for full‑chip level, tape‑out sign‑off requirements, checklists, and associated automation. 3 years of experience in people management, developing employees. Experience delivering silicon. Preferred Qualifications Master’s degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture. Experience in extraction of design parameters, QoR metrics, and analyzing data trends with knowledge of semiconductor device physics and transistor characteristics. Experience in engineering across physical design, top‑level implementation, GDS tape‑out. Ability to deliver silicon in advanced technology process nodes. Ability to lead cross‑functional teams. Responsibilities Lead and manage functional Static Timing Analysis (STA) team responsible for delivering system‑on‑chip (SoC) STA. Execute full chip timing sign‑off checklist, perform full chip STA, power recovery, timing ECO creation and oversee final timing sign‑off for SoC’s. Define SoC timing sign‑off process corners, derates, uncertainties and their trade‑offs. Drive clock tree planning and implementation for SoCs to achieve best energy, performance, and area. Collaborate with front‑end, Design for Test (DFT) and Computer‑aided design (CAD) teams for the design exploration and closure. Google is proud to be an equal‑opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity, or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google’s EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form. #J-18808-Ljbffr Google