UVM Digital Verification Engineer - FPGA/ASIC
$75k - $150kDraper Inc.
A nonprofit research and development organization in Cambridge, MA, is seeking a motivated UVM Digital Verification Engineer. The role involves tackling verification challenges within FPGAs and ASICs. Candidates should have 3-5 years of experience or relevant master's experience, focusing on skills such as integrated circuit design and problem-solving in a collaborative environment. The position offers a salary range of $75,000 to $150,000, plus benefits and opportunities for work-life balance. #J-18808-Ljbffr Draper Inc.
Vacancy posted 5 days ago
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