ASIC DFT Emulation Technical Lead
$186.9k - $267.7kCisco Systems
The application window is expected to close on: 10/20/2026Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received.Meet The TeamThe Common Hardware Group (CHG) delivers the silicon, optics, and hardware platforms for Cisco's core Switching, Routing, and Wireless products. We design the networking hardware for Enterprises and Service Providers of various sizes, the Public Sector, and Non-Profit Organizations across the world. Cisco Silicon One (#CiscoSiliconOne) is the only unifying silicon architecture in the market that enables customers to deploy the best-of-breed silicon from Top of Rack (TOR) switches all the way through web scale data centers and across service provider, enterprise networks, and data centers with a fully unified routing and switching portfolio. Come join us and take part in shaping Cisco's ground-breaking solutions by designing, developing and testing some of the most complex ASICs being developed in the industry. Your ImpactAs an ASIC DFT - Emulation Technical Lead, you will play a critical role in driving the DFT emulation strategy for Silicon One. You’ll architect state-of-the-art emulation environments, lead pre-silicon test plan execution, and validate complex scan, MBIST, and JTAG architectures on platforms like Palladium, Veloce, or Zebu. Partnering closely with front-end RTL, physical design, and ATPG teams, you will troubleshoot critical issues and ensure high-quality post-silicon pattern conversion. Your technical leadership and cross-functional collaboration will guarantee seamless silicon bring-up and optimal test coverage across next-generation hardware platforms.Minimum QualificationsBachelors + 8 years of related experience, or Masters + 6 years of related experience, or PhD + 3 years of related experiencePrior emulation experience on platforms such as Palladium, Veloce, or Zebu as well as experience with compilation and debug.Prior experience with Verilog and System Verilog.Prior experience with C/C++ and scripting skills with Tcl or Python/Perl.Preferred QualificationsPrior experience defining DFT Emulation strategy.Prior experience with JTAG protocol, scan architecture, MBIST and boundary scan.UVM and advanced System Verilog knowledge.Post Silicon validation and/or debugging experience.Why Cisco? At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint.Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere. We are Cisco, and our power starts with you. Message to applicants applying to work in the U.S. and/or Canada:The starting salary range posted for this position is $186,900.00 to $267,700.00 and reflects the projected salary range for new hires in this position in U.S. and/or Canada locations, not including incentive compensation*, equity, or benefits.Individual pay is determined by the candidate's hiring location, market conditions, job-related skillset, experience, qualifications, education, certifications, and/or training. The full salary range for certain locations is listed below. For locations not listed below, the recruiter can share more details about compensation for the role in your location during the hiring process.U.S. employees are offered benefits, subject to Cisco’s plan eligibility rules, which include medical, dental and vision insurance, a 401(k) plan with a Cisco matching contribution, paid parental leave, short and long-term disability coverage, and basic life insurance. Please see the Cisco careers site to discover more benefits and perks. Employees may be eligible to receive grants of Cisco restricted stock units, which vest following continued employment with Cisco for defined periods of time.U.S. employees are eligible for paid time away as described below, subject to Cisco’s policies:10 paid holidays per full calendar year, plus 1 floating holiday for non-exempt employees1 paid day off for employee’s birthday, paid year-end holiday shutdown, and 4 paid days off for personal wellness determined by CiscoNon-exempt employees** receive 16 days of paid vacation time per full calendar year, accrued at rate of 4.92 hours per pay period for full-time employeesExempt employees participate in Cisco’s flexible vacation time off program, which has no defined limit on how much vacation time eligible employees may use (subject to availability and some business limitations)80 hours of sick time off provided on hire date and each January 1st thereafter, and up to 80 hours of unused sick time carried forward from one calendar year to the nextAdditional paid time away may be requested to deal with critical or emergency issues for family membersOptional 10 paid days per full calendar year to volunteerFor non-sales roles, employees are also eligible to earn annual bonuses subject to Cisco’s policies.Employees on sales plans earn performance-based incentive pay on top of their base salary, which is split between quota and non-quota components, subject to the applicable Cisco plan. For quota-based incentive pay, Cisco typically pays as follows:.75% of incentive target for each 1% of revenue attainment up to 50% of quota;1.5% of incentive target for each 1% of attainment between 50% and 75%;1% of incentive target for each 1% of attainment between 75% and 100%; andOnce performance exceeds 100% attainment, incentive rates are at or above 1% for each 1% of attainment with no cap on incentive compensation.For non-quota-based sales performance elements such as strategic sales objectives, Cisco may pay 0% up to 125% of target. Cisco sales plans do not have a minimum threshold of performance for sales incentive compensation to be paid.The applicable full salary ranges for this position, by specific state, are listed below:New York City Metro Area:$186,900.00 - $307,800.00Non-Metro New York state & Washington state:$166,300.00 - $274,100.00* For quota-based sales roles on Cisco’s sales plan, the ranges provided in this posting include base pay and sales target incentive compensation combined.** Employees in Illinois, whether exempt or non-exempt, will participate in a unique time off program to meet local requirements.Job SummaryJob number: 2019597Date posted : 2026-08-04Profession: Product and EngineeringEmployment type: Full time
$186.9k - $267.7k
...developing and testing some of the most complex ASICs being developed in the industry. Your ImpactAs an ASIC Technical Lead, you will stand at the absolute forefront of... ...architecture. By driving cutting-edge Design-for-Test (DFT) strategies and pioneering custom IP solutions,...SuggestedFull timeTemporary workLocal areaWorldwideFlexible hours- Title - Lead ASIC DFT Engineer Location: San Jose, CA. Visa: USC/GC Job Description Experience: 10+ years of hands‑on experience in ASIC... ...for complex ASIC and SoC designs . This role requires deep technical ownership across DFT architecture, scan insertion, ATPG, MBIST...Suggested
$186.9k - $267.7k
...will be in the Silicon One development organization as an ASIC Technical Leader- DFT. You will work with Front-end RTL teams, backend physical design... ...next generation networking chips. You will help lead to drive the DFT and quality process through the entire Implementation...SuggestedFull timeTemporary workLocal areaFlexible hours$214.1k - $309.8k
...will be part of the Silicon One development organization as an ASIC Technical Lead- MBIST engineer. As a member of this team you will be... ...12+years (or Master's with 10+ years) of experience in ASIC DFT.Prior experience with memory architectures (SRAM, DRAM, etc....SuggestedFull timeTemporary workLocal areaFlexible hours- Lead Engineering Talent Acquisition | Helping Engineers Land Roles at Top U.S. Firms Required Skills & Qualifications Familiarity with the Siemens suite of DFT tools DFT insertion for SCAN (with SSN) and MBIST MBIST Repair Implementation and Verification Generating...SuggestedContract work
$143.8k - $230k
...Engineer to serve as the Chip Lead for our next-generation silicon... ...role, you will be the primary technical anchor responsible for the top... ...direct industry experience in ASIC/SoC digital design, with a... ...interconnects).Familiarity with DFT (Design for Test) planning, including...Full timeLocal area$186.9k - $267.7k
...post silicon validation tests in the lab.Minimum QualificationsBachelor’s degree in Electrical or Computer engineering and 8+ years of ASIC Design experience, or Master’s degree in Electrical Engineering or Computer Engineering and 6+ years of ASIC Design experience, or...Full timeTemporary workLocal areaFlexible hours$186.9k - $267.7k
...You will be in the Silicon One development organization as an ASIC design verification engineer in San Jose, CA. You collaborate closely... ...cross-functional teams to verify the ASIC in simulation, in emulation, and during ASIC bring-up. Your Impact:Maintaining existing DV...Full timeTemporary workWork at officeLocal areaFlexible hours$186.9k - $267.7k
...revolutionary solutions by designing, developing and testing some of the most complex ASICs being developed in the industry.Your Impact:As a technical leader, you will own and drive end-to-end DFT flow architecture, building and maintaining scalable CAD infrastructure that...Full timeTemporary workLocal areaFlexible hours$214.1k - $309.8k
...position provides high-level technical leadership for the Silicon One... ...bridging the gap between advanced DFT architecture, silicon quality,... ...to drive DPPM to industry-leading lows.Data-Driven Process OptimizationMonitor... ....Deep knowledge of the full ASIC development lifecycle,...Full timeTemporary workWork at officeLocal areaFlexible hours$186.9k - $267.7k
...the planning and execution of ASIC verification for complex networking... ...verification efforts.Provide technical leadership and mentorship to... ...with architecture, RTL, emulation, FPGA, and post-silicon teams... ...and successful silicon bring-up.Lead complex debug efforts, perform...Full timeTemporary workLocal areaFlexible hours- ...of SystemVerilog/Verilog (for correlating failures to rtl if needed) Good to have (not critical): * Scan insertion * RTL DFT Verification capability (MBIST, clocking etc..) * DFT DRC (spyglass) \nCompany Description Who We Are: Quest Global delivers world...
- ...AI breakthroughs, or bringing leading edge products to market, every... ...impact.You're an experienced ASIC/FPGA design engineer who has delivered... .... Instead, you'll serve as a technical partner to chip leads across... ...test and DFT methodologiesSilicon bring-up...
$175k - $250k
...thought impossible. We are seeking a seasoned and visionary Technical Lead, Network Software Development. This role involves strategic... ...Network and Device management - interfacing with hardware (ASIC/FPGA and other devices), switch management, configuration, telemetry...Remote workWorldwideFlexible hours$171.6k - $245k
...you’ll join forces with expert ASIC design teams in the Central... ...Silicon Operations focusing on leading the design, development, and testing... ...state-of-the-art trends in DFT insertion techniques,... ...across many parts of Cisco's technical entities to provide bleeding-edge...Full timeTemporary workWork at officeLocal areaFlexible hours$2,500 per month
...investors and staffed by leading engineers, Etched is... ...our AI/ML accelerator ASICs across their entire Lifecycle... ..., from pre-silicon emulation and FPGA prototyping through... ..., architecture, DFT, and driver teams to ensure... ...we expect all of our technical staff to contribute to...Work at officeRelocation package$239.2k
...McCarthy Blvd., Suite 200, Milpitas, CA 95035, is seeking to hire a Technical Lead Manager in SSD Firmware. Job Duties Lead SSD Firmware and... ...cross‑functional architecture reviews and collaborate with ASIC and software teams to define and deliver integrated firmware/hardware...- ...Description Job Description Network Platform Software Development- Technical Lead San Jose, CA/US Remote About Arrcus Arrcus was... ..., policing, shaping, ACL, ECN, and WRED. • Work with ASIC families (e.g., BCM XGS, BF Tofino) and develop software using...Work experience placementWork at officeRemote workFlexible hours
$157.3k - $212.8k
...world-class server infrastructure; we’re handling massive scale and rapid integration of emergent technologies. We’re looking for an ASIC Design Engineer to help us trail-blaze new technologies and architectures, while ensuring high design quality and making the right...InternshipLocal areaWork from homeFlexible hours$171.6k - $245k
...to close on: 09/24/2026ASIC Engineering Technical Leader (onsite) - 2014979*position requires... ...activity at San Jose CA office*Cisco ASIC Engineers develop and work with Next Generation... ...System Level Test Engineering Technical Lead to validate and ensure the quality of...Full timeTemporary workWork at officeLocal areaFlexible hours$180k - $225k
...Renesas Electronics, a leading global semiconductor company, is rapidly scaling its AI... ...) division seeks an experienced Customer Technical Lead to shape the next generation of datacenter... ...related to CPU’s and other high current ASIC’s ~ Experience with multiphase VR’s or...Full time$183k - $247.6k
...and software stacks enable us to take on technical challenges that have never been seen before... ...technologies. We’re looking for an ASIC Design Eengineer to help us trail-blaze new... ...SOC, ensure correct clock/reset/functional/DFT signal routing- Analyze design, microarchitecture...Local areaFlexible hours- ...Technical Lead Job Title: Technical Lead (Job ID: TLVL26) Job Location: WinWire Technologies, Inc., 5201 Great America Pkwy., Suite 259, Santa Clara, CA 95054 & various unanticipated locations in the US Design and implement end-to-end architecture for Salesforce...Remote workRelocation
$207k - $259k
...and optimize the turboshaft design for the integrated unitManage technical, certification, program and other risks to ensure we are... ...Extremely self-motivated with the ability to work independently and lead technical initiativesStrong written and verbal communication skills...Local areaVisa sponsorshipNight shift- ...writing functional or performance models of hardware such as SoCs, ASICs, GPUs, CPUs, or IP blocks. Familiarity with SoC, CPU, GPU,... ...with SystemC or TLM-based modeling, RTL simulation or emulation correlation, performance-model development or calibration, modern...Full timeFlexible hours
- ...Senior Technical LeadDesign, build, and integrate complex mechanical reliability/stress-test fixtures for product testing, with the fixtures designed to interface directly with our CT (computed tomography) scanning systems. The goal is to stress test products under controlled...Flexible hours
- ...NVIDIA is seeking a Senior Developer Relations Manager to lead developer and partner adoption of Cosmos 3 and the Cosmos world foundation... ...model family across the Robotics ecosystem. You will cultivate technical relationships with partners, AI labs, and the Cosmos Coalition...
$171.6k - $245k
...digital world. Your Impact Hardware design technical lead is a key member of the Cisco Purpose... ...hardware based on Silicon One and/or merchant ASIC.Responsible for system and board level... ...work with multiple groups including ASIC, DFT, Signal Integrity, software, Diagnostics...Full timeTemporary workLocal areaFlexible hours$114.6k - $234.6k
...Layer Debugging Play a leading role in initial board, device... ..., JTAG, logic analyzers, emulators, and platform instrumentation... ...engineering improvements. Technical Leadership Own technically... ...protocols. CPU, GPU, SoC, ASIC, or FPGA-based systems....Temporary workFlexible hours$177.9k - $284.7k
...functionality. Nextest engineering teams are characterized by deep technical skills working with both software and hardware. Our Engineers... ...software that directly interacts with hardware (FPGAs and ASICs)Knowledge of Windows and experience with Visual Studio requiredFamiliarity...Local areaRelocationFlexible hours
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