US_West | Electrical/Electronics & Semiconductors Engineer_L2

Job Description

Job Description

Role Name: ASIC Engineering Technical Leader
Work Location: San Jose, CA (Onsite)

• Lead the implementation of SSN-based test-flow DFT architectures, including scan insertion, compression/decompression logic, memory BIST, and logic BIST.
• Utilize Siemens Tessent tools for RTL and gate-level netlist DFT implementation.
• Generate and deliver ATPG test patterns for:
  • Stuck-at fault models
  • Transition fault models
  • Cell-aware fault models
  • Path-delay fault models
• Drive scan-based diagnosis methodologies for silicon failure debugging.
• Provide post-silicon testing, validation, and troubleshooting support.
• Evaluate design readiness for scan insertion using RTL and physical-design Scan Design Rule Check (DRC) tools.
• Integrate and verify Design-for-Test (DFT) fabrics and IP within subsystems.
• Perform and debug non-timing and back-annotated timing (SDF) gate-level simulations.
• Develop test scripts, automate engineering processes, and analyze data using programming languages such as Python, Tcl, or C++.
• Support DFT execution throughout the ASIC development lifecycle, including design, verification, tapeout, and post-silicon validation.

• Bachelor’s degree with 8+ years of related experience, OR
• Master’s degree with 6+ years of related experience, OR
• PhD with 3+ years of related experience.
• Prior experience working with ASICs.
• Hands-on experience with scan insertion and DFT setup, integration, and validation.
• Experience implementing DFT architectures, including:
  • Scan insertion
  • Compression/decompression logic
  • Memory BIST
  • Logic BIST

• 10+ years of experience working with ASICs.
• 10+ years of experience with scan insertion and DFT setup, integration, and validation.
• 3+ years of experience with SSN.
• Experience driving ASIC DFT execution from concept through tapeout.
• Experience working with ATE testers and test engineering teams.
• Strong RTL knowledge with the ability to understand and debug DFT-related issues.
• Ability to solve complex technical problems, including clock-domain crossing (CDC) issues.
• Familiarity with advanced silicon processes and technology nodes designed for high-speed and low-power applications.
• Strong experience implementing or integrating design blocks using Verilog/SystemVerilog.