Logic Design Engineer

Overview Intel is shaping the future of technology with a focus on AI, analytics, and cloud‑to‑edge solutions. The multiprotocol SerDes design team in our Santa Clara office seeks a senior logic design engineer to support next‑generation products. Responsibilities Logic design of High Speed SerDes including RTL coding and simulation for IP that generates cell libraries, functional units, IP blocks, and subsystems for full chip integration. Participate in defining architecture and microarchitecture features of the block. Apply strategies, tools, and methods to write RTL and optimize logic to meet power, performance, area, and timing goals while ensuring design integrity for physical implementation. Review verification plans and implementations to ensure correct feature verification and execute corrective measures for failing RTL tests. Support SoC customers to ensure high‑quality IP integration and verification. Drive quality‑assurance compliance for smooth IP SoC handoff. Key Attributes Excellent communication skills, expected to drive clarity across partners and managers. Strong teamwork abilities within a small team environment. Analytical and problem‑solving skills with the ability to draw independent conclusions. Minimum Qualifications Bachelor's in Electrical/Computer Engineering with 8+ years of experience, OR Master's in Electrical/Computer Engineering with 6+ years of industry experience. 5+ years of mixed‑signal design experience, specifically High Speed SerDes design and architecture. Detailed knowledge of SerDes PMA and PCS layers. Experience with post‑silicon validation and support of High Speed SerDes IP. Ability to read and interpret technical specs to develop microarchitecture and implement RTL design in SystemVerilog. Strong background in computer system architecture and digital design. Proficiency in OVM/UVM methodology to collaborate with validation designers for content development. Preferred Qualifications Experience with automated place‑and‑route teams to convey constraints and close timing issues. Proficiency in one or more scripting languages (TCL, Perl, Python, Ruby). Job Type and Location Experienced Hire – Shift1 (United States). Primary location: Santa Clara, California. Additional locations may apply. Position of Trust This role is a Position of Trust. Successful candidates will be required to pass an extended background investigation, including education, SEC sanctions, and criminal checks. Benefits We offer a competitive compensation package including salary, stock bonuses, and benefits such as health, retirement, and vacation. Total compensation for this role in the U.S. ranges from $220,920 to $311,890, depending on location and experience. EEO Statement All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. #J-18808-Ljbffr Intel Corporation