RTL Design Engineer, Silicon (ASIC/IP)
Google Inc.
Google Mountain View, CA, is seeking an RTL Design Engineer in Silicon to contribute to custom silicon powering Google devices. You will define microarchitecture, integrate IP, and perform RTL coding and verification. Requirements include a Bachelor's in EE/CE/CS or related field, 4 years of IP development or integration experience, and proficiency in Verilog or VHDL; scripting in Python or Perl is preferred. Master/PhD plus ASIC/DFT experience preferred. #J-18808-Ljbffr Google Inc.
Vacancy posted 3 days ago
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