Verification Lead Memory Controller (CHI-G / DFI)

Role: Verification Lead Memory Controller (CHI-G / DFI)
Location: San Jose, CA




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About The AES Group
The AES Group is a premier technology and engineering consulting company that has been bringing businesses and talent together for over 20 years to deliver innovative solutions that have the greatest positive impact on society. AES has helped over 40 business enterprises, including Fortune 500 companies, engage their customers, empower their employees, and transform their business operations with the power of cloud, data, AI, engineering, and other emerging technologies.

Role Summary
We are seeking a Verification Lead to own the verification strategy, planning, and execution for the Memory Controller subsystem, including CHI-G protocol compliance and DFI interface verification. This role will lead a team of verification engineers through architecture updates driven by design changes to the memory controller, ensuring full functional coverage and sign-off quality.







Key Responsibilities
Define and own the overall verification strategy and test plan for the memory controller, covering new CHI-G and DFI-related design changes
Lead development of UVM-based testbenches, scoreboards, and checkers for CHI-G coherency protocol and
DFI timing/command verification
Drive coverage closure (functional, code, and assertion-based) and sign-off criteria for the modified design
Coordinate with design engineers to understand RTL changes and translate them into updated verification
plans and regression suites
Own formal verification strategy for protocol-critical paths (CHI-G coherency, DFI handshakes) where
applicable
Manage regression infrastructure, triage failures, and drive bug closure with design and DFT teams
Mentor and manage a team of verification engineers; review testbench architecture, code, and coverage plans
Report verification status, risks, and schedule to program management and cross-functional stakeholders
Own verification documentation: test plans, coverage models, and sign-off reports







Required Qualifications
Bachelor's/Master's in Electrical Engineering, Computer Engineering, or related field
10+ years of design verification experience, with 3+ years in a lead/management capacity
Strong hands-on experience verifying memory controllers (DDR4/DDR5/LPDDR)
Deep knowledge of ARM CHI/CHI-G protocol verification (coherency scenarios, snoop filtering, ordering
rules)
Experience verifying DFI-compliant PHY interfaces (command/data timing, calibration sequences)
Expert-level SystemVerilog/UVM skills; experience building verification environments from scratch and
extending existing ones
Experience verifying subsystem with APB/AHB/AXI4/ACE interfaces
Experience with coverage-driven verification methodology and sign-off processes
Proven track record leading verification teams through tapeout







Preferred Qualifications
Experience with formal verification tools for protocol/coherency checking
Experience with post-silicon validation correlation to pre-silicon verification
Exposure to AI/LLM-assisted verification tooling (test generation, coverage analysis, debug assistance)