Principal/Lead Design Engineer Memory Controller-(CHI-G / DFI)

Role: Principal/Lead Design Engineer Memory Controller- (CHI-G / DFI)
Location: San Jose, CA




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Role Summary
We are looking for a Principal Design Engineer to lead RTL development and architecture updates for our Memory Controller subsystem, with deep expertise in the ARM CHI-G (Coherent Hub Interface Gateway) protocol and DDR/LPDDR/HBM PHY-facing DFI (DFI Interface). This role owns modifying and extending an existing memory controller design to accommodate new architectural requirements, protocol updates, and performance targets.







Key Responsibilities
Modify and extend an existing memory controller RTL design to support new CHI-G protocol requirements
and DFI interface changes
Own microarchitecture updates for command scheduling, arbitration, QoS, and bank/rank management
within the memory controller
Design and integrate CHI-G request/response/snoop channel logic, ensuring protocol compliance and
coherency correctness
Develop and maintain DFI-compliant interface logic (command, write/read data, timing parameters) to PHY
Analyze impact of new features on timing, power, and area; drive RTL changes through synthesis and STA
closure
Collaborate with verification, DFT, and physical design teams to ensure the modified design meets
functional and PPA (Power, Performance, Area) goals
Debug pre-silicon and post-silicon issues related to memory controller behavior, coherency, and interface
timing
Produce/update microarchitecture specs, interface timing diagrams, and design documentation reflecting the
new changes
Participate in design reviews and mentor junior engineers on CHI-G/DFI concepts







Required Qualifications
Bachelos/Masters in Electrical Engineering, Computer Engineering, or related field
8+ years of RTL design experience in SystemVerilog/Verilog for SoC subsystems
Hands-on experience with memory controller design (DDR4/DDR5/LPDDR) or equivalent
Working knowledge of ARM CHI/CHI-G protocol (coherency, request/response/snoop channels)
Working knowledge of APB/AHB/AXI4/ACE interfaces
Experience with the DFI specification and PHY-facing timing/command interfaces
Experience modifying/extending existing large RTL codebases (not greenfield-only experience)
Familiarity with synthesis, timing closure, and low-power design techniques
Strong debugging skills using simulation waveforms, formal tools, and lab equipment







Preferred Qualifications
Exposure to DFT, post-silicon bring-up, or PCB-level memory subsystem validation
Familiarity with UVM-based verification flows (to collaborate effectively with verification teams)
Experience with AI/LLM-assisted RTL development or design productivity tooling