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  •  ...methodology, design and implementation of critical Design-for-Test (DFT) and Design-for-Debug (DFD) features for complex state-of-the-art...  ...Good object oriented programming skillsDigital circuits and VLSI knowledgeStrong problem solving skillsGood written and oral communication... 
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    AMD

    Markham, IL
    2 days ago
  • $121.9k - $195k

     ...have a Candidate Account, please Sign-In before you apply.Job Description:We are seeking a Senior Digital VLSI Design Engineer with deep expertise in Synthesis, DFT, Clock Domain Crossing (CDC) and Reset Domain Crossing (RDC) sign-off for high speed complex IPs to be... 
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    Full time
    Local area

    Broadcom

    San Jose, CA
    2 days ago
  •  ...DeSantis and Dave Brown: AWS re:Invent 2025 - Deep Dive into the AWS Nitro System re:Invent 2025 - AWS Graviton Reducing design for test (DFT) effort with Tessent Streaming Scan Network (SSN) - Dan Trock, Amazon Key job responsibilities* Design and implement advanced Design-... 
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    Amazon

    Illinois
    22 hours ago
  • $196k - $310.5k

     ...a senior member in our team, you will work on innovating in the DFT Power, Thermal & Voltage Noise Methodology areas.This will include...  ...in DFT design & powerUnderstanding of fundamental DFT topics and VLSI areas of power, timing & voltage noiseExperience in Power Analysis... 
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    Full time

    Nvidia

    Santa Clara, CA
    4 days ago
  •  ...advance your career. THE ROLE:We are seeking an experienced SoC DFX Engineer to help define, design, and verify robust Design for Test (DFT) and Design for Debug (DFD) solutions for complex, high‑performance SoCs. In this role, you will collaborate closely with... 
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    AMD

    Austin, TX
    4 days ago
  • Job ID: 21306624Reference Number: 24-00165Title: DFT EngineerLocation: Iselin, NJ, 08830Posted Date: 2024-02-08Company: HAN StaffingDFT Engineer
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    HAN Staffing

    Iselin, NJ
    2 days ago
  •  ...to make an impact on the world of technology.We are looking for SoC/ASIC Digital Design Engineer with experience in Design for Test (DFT). An intimate knowledge and experience in scan chain insertion, compression scan technologies, memory built-in self-test (MBIST) and... 
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    Full time

    Cadence Design Systems

    San Jose, CA
    4 days ago
  • $168k - $258.75k

     ...you to help us accelerate the next wave of artificial intelligence. We serve as the central program management function for NVIDIA’s VLSI Engineering organization, providing the structure and insight needed to deliver world-class silicon. We align roadmaps across all... 
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    Full time

    Nvidia

    Santa Clara, CA
    1 day ago
  • Overview We are looking for talented and experienced VLSI Design Engineers/Micro-architects. As a VLSI Digital Design Engineer/Micro-architect...  ...development, debug support, and functional coverage closure; DFT team to ensure design is scan-insertable, supports ATPG, BIST,... 
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    Retym, Inc

    Austin, TX
    5 days ago
  • $163k - $236k

    Partner with cross-functional teams to architect, implement, and verify design-for-test (DFT) solutions for advanced CPU designs.Pioneer custom DFT methodologies using industry-standard EDA tools to accelerate turnaround times and test coverage.Develop, debug, and optimize... 
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    Google

    Austin, TX
    4 days ago
  • We are looking for an experienced DFT Engineer with strong expertise in DFT architecture, implementation, ATPG, and SoC verification....  ...practical experience. #Hiring #DFT #DFTEngineer #Broadcom #ASIC #VLSI #Semiconductor #ATPG #MBIST #JTAG #SLT #Tessent #TestKompress #DFTMax... 
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    Value Innovation Labs

    Mountain View, CA
    2 days ago
  • $168k - $264.5k

     ...make a lasting impact on the world.NVIDIA is seeking a talented Software Engineer to join our small team building custom, high-impact VLSI CAD software in a technically challenging and highly visible domain. This is a full-cycle role with meaningful opportunities to... 
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    Full time
    Worldwide

    Nvidia

    Santa Clara, CA
    1 day ago
  • $129.4k - $207k

     ...Candidate Account, please Sign-In before you apply.Job Description:As a member of our team, you will be responsible for various aspects of DFT, including MBIST and scan insertion, ATPG, ATE pattern development, and yield analysis.Key Responsibilities:Work closely with the ATE... 
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    Full time
    Local area

    Broadcom

    Austin, TX
    3 days ago
  • $152.5k - $219.2k

     ...on Design-for-Test. You will work with Front-end RTL teams, backend physical design teams to understand chip architecture and drive DFT requirements early in the design cycle. As a member of this team you will also be involved in crafting groundbreaking next generation... 
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    Temporary work
    Local area
    Flexible hours

    CISCO Systems

    San Jose, CA
    3 days ago
  • $136k - $218.5k

     ...to join us today.Design-for-Test Engineering at NVIDIA works on groundbreaking innovations involving crafting creative solutions for DFT architecture, verification and post-silicon validation on some of the industry's most complex semiconductor chips. What you'll be doing... 
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    Full time

    Nvidia

    Santa Clara, CA
    5 days ago
  • $136k - $218.5k

     ....Are you excited to architect and build the automation infrastructure behind next-generation silicon design? We’re seeking a Senior VLSI Library Methodology Engineer to join our team and drive the development, specification, and implementation of scalable systems. These... 
    Full time

    Nvidia

    Santa Clara, CA
    3 days ago
  • DFT EngineerYou will join a team working on leading-edge projects in the Business Unit (BU) MCU & MPU Engineering & Design Enablement (MMEDE). MMEDE BU brings the technology and ecosystem relationships for next gen automotive Processing, Edge Processing & Radar Processing... 
    Full time
    Work at office
    Local area

    NXP Semiconductors

    Austin, TX
    5 days ago
  • Job description Senior DFT EngineerMoTek Technologies has an immediate opening for a Senior DFT Engineer:The ideal candiate will be responsible for DFT flows and implementation Run RTL, gate, and gate with SDF simulations to confirm correct functionality of DFT logic. Generate... 
    Immediate start

    MoTek Technologies

    San Jose, CA
    5 days ago
  •  ...videos to learn more about Annapurna Labs.AWS re:Invent 2025 - Keynote with Peter DeSantis and Dave Brown: Reducing design for test (DFT) effort with Tessent Streaming Scan Network (SSN) - Dan Trock, Amazon Key job responsibilitiesIn this highly-visible role you will assume... 
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    Amazon

    Illinois
    2 days ago
  • $141.91k - $200.34k

    Job Details:Job Description: The Role and ImpactAs a DFT Design Engineer, you will play a pivotal role in shaping Intel's silicon solutions. Your contributions will directly influence the quality and efficiency of Intel's products, ensuring seamless integration of Design... 
    Full time
    Local area
    Immediate start
    Shift work

    Intel

    Austin, TX
    4 days ago
  • $210k - $340k

     ...SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars.PRINCIPAL DFT ENGINEER (SILICON ENGINEERING)At SpaceX we’re leveraging our experience in building rockets and spacecraft to deploy Starlink, the... 
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    Temporary work
    Worldwide
    Weekend work

    SpaceX

    Irvine, CA
    5 days ago
  • $168k - $264.5k

    We are now looking for a DFT Methodology Engineer!NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently... 
    Full time

    Nvidia

    Santa Clara, CA
    2 days ago
  • We are looking for a talented and experienced DFT Tech Lead. As a DFT Tech Lead you will work closely with all other design teams - backend, VLSI, verification and analog, fully responsible for defining, implementing, and deploying advanced design-for-test (DFT) methodologies... 

    Retym, Inc

    Austin, TX
    5 days ago
  • $122.44k - $232.19k

     ...portfolio, a world-class design ecosystem, and an operationally resilient global manufacturing supply chain.Position OverviewWe seek a DFT Application Engineer to provide technical support to Intel Foundry Services customers on PDKs, DFT/DFM insertion, and ATPG validation... 
    Full time
    Internship
    Local area
    Immediate start
    Shift work

    Intel

    Santa Clara, CA
    1 day ago
  • $136k - $218.5k

     ...Software Engineers to work on developing and deploying AI agents that leverage machine learning models to solve complex problems in VLSI design. The ideal candidate will have a strong background in computer science, electrical engineering, or related field, with experience... 
    Full time

    Nvidia

    Santa Clara, CA
    3 days ago
  • As a DfT engineer, you will join a highly experienced team. Your key responsibilities will be:1) Closely collaborate with Product Definer, Analog Design Lead, Digital Design Lead, Test Lead, Product Engineer, Quality Engineer, Validation Engineer - to identify the superset... 
    Full time
    Work at office
    Local area
    Relocation
    3 days per week

    NXP Semiconductors

    Chandler, AZ
    1 day ago
  • $163k - $236k

    Develop and document DFT strategy, architecture and test sequences, including hierarchical DFT, MBIST, ATPG and I/JTAG, and associated boot up and execution sequences.Complete all Test Design Rule Checks (TDRC) and Design changes to fix TDRC violations to achieve high test... 
    Worldwide

    Google

    Sunnyvale, CA
    4 days ago
  •  ...industry leading CPU’s and caches that are the foundation of AMD’s server, client, and gaming business. We are looking for an experienced VLSI physical design engineer to join this innovative team as a technical expert. The candidate will be a key contributor and leader for... 

    AMD

    Fort Collins, CO
    5 days ago
  •  ...diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE:As a member of the Cores DFT Team, the successful candidate will own the ATPG responsibilities for the next generation of AMD high-performance cores.THE PERSON:... 

    AMD

    Santa Clara, CA
    4 days ago
  • $72k - $108k

     ...RESPONSIBILITIES: RTL design and verification in Verilog, RTL linting, clock domain crossing (CDC) analysis, design integration, synthesis, DFT, timing analysis and closure Balance design trade-offs with modularity, scalability, power, area, and performance. Interface with... 

    Vaia GmbH

    Milpitas, CA
    5 days ago