Design Verification Engineering

SoC Design Verification, SystemVerilog, UVM, Object-Oriented Programming, Python, C++, Java, Digital Design, Computer Architecture, Networking Protocol, HVL, Cellular Protocol, FW-HW Interaction, Multi-chip Debug, Coverage-driven Verification, AIML Methodology

Computers and Electronics Manufacturing

Description

Description Do you have a passion for invention and self-challenge? This position gives youthe opportunity to be a part of one of the most innovative and key projects thatApple’s Silicon Engineering Group has embarked upon to date. As part of ourteam, you will have the opportunity to take the lead and contribute to verifyinga set of sophisticated SoCs that are driving Apple’s flagship Cellular 5Gplatform. As a member of this team you will integrate multiple sophisticatedIP-level DV environments, craft highly reusable UVM TB, implement effectivecoverage-driven and advised test infrastructure, deploy new tools, develop anddeploy AIML methodology, and implement ideas to improve the quality of tape-outreadiness of all our chips. By collaborating with other product developmentgroups across Apple, you can push the industry boundaries of what complex SoCscan do and improve the product experience for our customers across the world!You will be able to learn all aspects of a large-scale SoC, different types ofSoC architecture, many high-speed layered protocols, the industry’s standardmethodologies on low-power architecture, outstanding DV methodology,verification on accelerated platforms, knowledge of cellular protocol, FW-HWinteractions, complexities of multi-chip SoC debug architecture, etc.DESCRIPTIONAs a Design Verification Engineer on our team, you'll be at the center of theverification effort within our silicon design group responsible for crafting andproductizing innovative Cellular SoCs! This position requires someonecomfortable with all areas of SoC design verification engineering. We arelooking for someone who thrives in a dynamic multi-functional organization, isnot afraid to debate ideas openly, and is flexible enough to shift withinconstantly evolving requirements.MINIMUM QUALIFICATIONSBachelors degree required Demonstrated knowledge of object-oriented programmingprinciples through coursework, research, or project experience in any OOP-basedlanguage (e.g., Python, C++, Java, or SystemVerilog). Coursework in DigitalDesign.PREFERRED QUALIFICATIONSMSEE, MSCS or beyond is preferred. Coursework in Computer Architecture,Networking Protocol. Hands-on experience developing UVM-based testbenches inSystemVerilog, demonstrating applied understanding of object-orientedprogramming. Experience in Digital Design. Experience in Developing ReferenceModel of DUT and Verification using HVL. Excellent communication,problem-solving skills, and the desire to seek diverse challenges.

Responsibilities

Responsibilities The engineer will lead and contribute to the verification of sophisticated SoCs for Apple's cellular 5G platform. Responsibilities include developing UVM testbenches, implementing coverage-driven infrastructure, and deploying AIML methodologies to ensure tape-out readiness.

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