Silicon RTL Design Engineer — High-Impact IP & ASIC
Google in Mountain View, CA is seeking a Mid-level RTL Design Engineer to drive micro-architecture definition and IP integration for an ASIC/subsystem. You will code in RTL languages, perform complex simulations, and contribute to synthesis, timing, and power closure for silicon bring-up. The role requires 5+ years in RTL design, IP integration, and scripting with Perl or Python, with a bias toward low-power and high-performance designs. Eligible for base salary with bonus and equity. #J-18808-Ljbffr Google
Vacancy posted 2 days ago
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