Senior Front End Design Engineer (Microarchitecture)

Cerebras Systems builds the world's largest AI chip, 56 times larger than GPUs. This architecture allows Cerebras to deliver industry-leading training and inference speeds, over 10 times faster than GPU-based hyperscale cloud inference services. This order of magnitude increase in speed transforms the user experience of AI applications, unlocking real‑time iteration and increasing intelligence via additional agentic computation. Cerebras works with leading model labs, global enterprises, and cutting‑edge AI‑native startups. OpenAI recently announced a multi‑year partnership with Cerebras to deploy 750 megawatts of scale, transforming key workloads with ultra high‑speed inference. About the Role As a senior front‑end design engineer, you will be a key part of the world‑class team designing and developing the next generations of the Cerebras Wafer Scale Engine (WSE). This role requires deep expertise in RTL design and integration, with a strong focus on delivering high‑performance, power‑efficient, and scalable solutions. You will collaborate closely with the design verification, physical design, software and system teams to bring innovative semiconductor architectures from concept to production, addressing the unique challenges of building WSE systems. Responsibilities Drive all aspects of chip design, including Functional Specification, Micro‑architecture, RTL development, and synthesis. Work closely with the PD team for design closure to meet PPA goals. Collaborate with Design Verification and DFT teams to achieve the best functional and test coverage. Work with software and system teams to understand opportunities to deliver optimal performance and feature set for the product. Debug silicon‑level functional, timing, and power issues during bring‑up. Requirements Master’s degree in Computer Science, Electrical Engineering, or equivalent. Experience of 8+ years delivering complex, high‑performance, high‑quality RTL designs. Experience with front‑end chip integration and third‑party IP integration. Demonstrated experience in networking, high‑performance computing, machine learning, or related fields. Proven track record of multiple silicon successes. Experience collaborating with external vendors. Networking stack experience including TCP/IP, RDMA, and Ethernet. Knowledge of PCIe, CPU interfaces, and Serdes technology. Working knowledge of scripting tools: Python and TCL. Assets Experience with FPGA development toolchain, including place and route, floor planning, and timing analysis. Experience managing an external ASIC vendor through the product development cycle. The base salary range for this position is $250,000 to $300,000 annually. Actual compensation may include bonus and equity, and will be determined based on factors such as experience, skills, and qualifications. Location Sunnyvale, CA Cerebras Systems is committed to creating an equal and diverse environment and is proud to be an equal opportunity employer. We celebrate different backgrounds, perspectives, and skills. We believe inclusive teams build better products and companies. We try every day to build a work environment that empowers people to do their best work through continuous learning, growth and support of those around them. This website or its third‑party tools process personal data. For more details, review our CCPA disclosure notice. #J-18808-Ljbffr Cerebras