IC Packaging Design Engineer

Job Title IC Packaging Design Engineer Location Chandler, AZ or Hillsboro, OR (100% Onsite) Duration Long-Term Contract (12+ Months) Employment Type C2C / W2 Openings 4 Job Description We are seeking experienced IC Packaging Design Engineers with strong expertise in package substrate design and advanced package layout. The ideal candidate should have hands‑on experience with Siemens (Mentor) Xpedition (XPD) or Cadence Allegro Advanced Package Designer (APD/SiP) and a solid understanding of IC package design methodologies. Required Qualifications Bachelor's or Master's degree in Electrical/Electronics Engineering. Senior Level: 10+ years of IC Packaging / Package Design experience. Mid Level: 4-6+ years (MS) or 6+ years (BS) of relevant experience. Strong hands‑on experience with Siemens (Mentor) Xpedition (XPD) (Preferred). Experience with Cadence Allegro APD / SiP is also acceptable. Strong understanding of package substrate design and layout. Required Skills IC Package Physical Design & Layout Substrate Design & Layout SI/PI Aware Design Implementation Design Rule Compliance (DRC) Design for Performance, Manufacturability, Yield & Reliability Package Floor Planning High-Speed Signal Routing Package Stack-up Design Cross-functional collaboration with SI/PI, Mechanical, and Manufacturing teams Preferred Skills FCBGA, FCCSP, SiP, or Advanced Packaging experience High-speed interfaces such as PCIe, DDR, HBM, or SerDes Strong problem-solving and debugging skills #J-18808-Ljbffr CORE Occupational Medicine