RTL Design Engineer, TPU Integration and Automation
$138k - $198kMinimum qualifications Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 4 years of experience in ASIC design, design automation, or a related field. Experience programming in Python and shell scripting, and experience with SystemVerilog or other hardware description languages. Experience with EDA tools and typical ASIC design and verification flows. Experience with version control systems (e.g., Git, Perforce) and with build systems (e.g., Bazel, Make). Experience with continuous integration systems (e.g., Jenkins). Preferred qualifications Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture. Experience with data visualization tools and dashboard creation. Understanding of digital design principles. Proven ability to work independently on end-to-end tasks and projects. Strong communication and collaboration skills, with the ability to work effectively in a team environment. Excellent problem‑solving and debugging skills. About The Job In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting‑edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide. We're the driving team behind Google's groundbreaking innovations, empowering the development of our cutting‑edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world‑leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. Individual pay is determined by factors including job‑related skills, experience, and relevant education or training. US: $138,000 - $198,000 (USD) + 15% bonus target + bonus + equity + benefits Responsibilities Own Compute IP releases to the SoC. Enhance scripts and flows for SoC releases to reduce manual effort and cycle time for IP releases. Use Python to improve efficiency and quality in top-level IP assembly, focusing on connectivity and configuration. Automate IP versioning and integration for cross‑project consistency. Liaise between Design and Physical Design teams to refine automation for reliable, high‑quality branch handoffs. Partner with multi‑functional teams to deploy automation for development pain points and document methodologies. Maintain automated systems to validate tool flows and design health. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form. #J-18808-Ljbffr Google
$138k - $198k
Google Inc. is seeking an RTL Design and Integration Engineer for its TPU team in Sunnyvale, CA. In this role, you will drive cutting-edge TPU technology, focusing on developing and integrating AI/ML hardware accelerators. The ideal candidate has a Bachelor's in Electrical...Suggested$138k - $198k
RTL Design and Integration Engineer, TPU and ML corporate_fare Google place Sunnyvale, CA, USA Apply Qualifications Bachelor's degree in Electrical... ...RTL solutions, RTL design methodologies, and automating front‑end engineering flows. About the Job In this role...SuggestedFull timeWorldwide- Google is looking for an RTL Design Engineer in Sunnyvale, California, to work on cutting-edge TPU technology. You will define microarchitecture, write performant RTL code, and collaborate closely to ensure functional correctness. This role impacts Google's AI advancements...Suggested
$138k - $198k
...Bachelor's degree in Electrical Engineering, Computer Engineering,... ...experience with digital design using SystemVerilog RTL. Experience with Computer... ...opportunity to drive cutting‑edge TPU (Tensor Processing Unit)... ...TPU architecture and its integration within AI/ML‑driven...SuggestedFull timeWorldwide$163k - $237k
...Bachelor's degree in Electrical Engineering, Computer Engineering,... ...of experience in ASIC design. Experience interacting with... ...Responsibilities Design RTL Intellectual Property (IP)... ...digital designs, focusing on TPU architecture and its integration within AI/ML‑driven...Suggested$163k - $237k
...s degree in Electrical Engineering, Computer Engineering,... ...of experience in ASIC design. Experience interacting... ...to drive cutting‑edge TPU (Tensor Processing Unit... ...TPU architecture and its integration within AI/ML‑driven systems... ...‑Transfer Level (RTL) design for our data center...Worldwide$138k - $198k
...acceleration, focusing on TPU technology that... ...subsystem’s design micro‑architecture... ...Develop SystemVerilog RTL to implement logic... ...in Electrical Engineering, Computer Engineering... ...Tcl, or Perl for automating design tasks and... ...Delay‑Locked Loop integration. Experience implementing...Full time$156k - $229k
...degree in Electrical Engineering, Computer... ...experience in ASIC design, including one project... ...Experience debugging RTL using Verdi/VCS and automating tasks via Python or... ...drive cutting-edge TPU (Tensor Processing Unit... ...architecture and its integration within AI/ML-driven...Full timeWorldwide$116k - $166k
...degree in Electrical Engineering, Computer Engineering,... ...year of experience in RTL design. Experience with digital... ...methodologies and automate front-end engineering... ...to drive cutting‑edge TPU (Tensor Processing Unit... ...architecture and its integration within AI/ML‑driven systems...Worldwide$138k - $198k
...Bachelor's degree in Electrical Engineering, Computer Engineering,... ...experience in high-performance ASIC design. Experience architecting or designing RTL solutions for digital systems... .... Design and verify TPU architecture and integration within AI/ML-driven systems....$163k - $237k
...to drive cutting‑edge TPU (Tensor Processing Unit... ...worldwide, and leverage your design and verification... ...TPU architecture and its integration within AI/ML‑driven systems... ...‑transfer level (RTL) IP with a focus on chip... ...s degree in Electrical Engineering, Computer Engineering,...Worldwide$138k - $198k
Google in Sunnyvale seeks a talented ASIC Design Engineer to drive cutting-edge TPU (Tensor Processing Unit) technology. You will enhance automation and work on impactful AI/ML applications, contributing to the development of custom silicon solutions. This role involves...$138k - $198k
...Bachelor's degree in Electrical Engineering, Computer Engineering,... ...2 years of experience with RTL Design. Experience with digital design... ...to drive cutting‑edge TPU (Tensor Processing Unit) technology... ...on TPU architecture and its integration within AI/ML‑driven systems....Worldwide$163k - $237k
Qualifications Bachelor's degree in Electrical Engineering, Computer Engineering, Computer... ...8 years of experience with digital design using SystemVerilog RTL. Experience with power,... ...unparalleled performance, efficiency, and integration. As an ASIC Design Engineer, you...Worldwide- ...company based in Sunnyvale, CA is seeking a PCIe Design Engineer to lead the design of high-performance ASICs... .../ML hardware acceleration. The role involves RTL development, managing comprehensive documentation, and integrating subsystem functionality within data center...
$138k - $198k
Google Inc. is seeking a High-Performance ASIC Designer in Sunnyvale, CA. The role involves designing RTL IP for AI and networking accelerators, working closely with various teams to ensure integration and performance. Candidates should possess a Bachelor's degree and...- ...Sunnyvale is seeking a skilled engineer to innovate in AI/ML hardware... ...involves developing SystemVerilog RTL for creating microarchitecture... ...with validation and design teams to ensure quality and achieve... ...to contribute to cutting-edge TPU technology and help shape the...Full time
- Google Inc. is seeking an experienced engineer in Sunnyvale, CA to lead the high-performance ASIC design and RTL execution for AI hardware. The successful candidate... ...experience in ASIC design and digital systems integration. Candidates will benefit from a competitive salary...
$163k - $237k
Senior Design and Integration Engineer, Cloud TPU Sunnyvale, CA, USA. Level: Mid. Job Summary Shape the future of... ...to develop test plans and debug RTL, and collaborate with Physical Design... ...Drive critical power optimization and automation initiatives across all on‑chip‑...$163k - $237k
Google Inc. in Sunnyvale, CA is seeking a Senior Design and Integration Engineer for Cloud TPU. In this role, you will shape the future of AI/ML hardware by... ...a Bachelor's degree in a related field and 8 years of RTL design experience. Compensation ranges from $163,000 to...$138k - $198k
...ML hardware acceleration, particularly in TPU technology. The successful candidate will have a strong background in ASIC RTL design and responsibilities include creating micro... ...hold a Bachelor’s degree in Electrical Engineering or a related field and possess a minimum of...- Google Inc. is seeking a Soc Design Engineer in Sunnyvale, California, to shape the future of AI and ML hardware acceleration. This role involves driving TPU technology and working on SoC-level RTL design for advanced AI applications. The ideal candidate will have a Bachelor...
- Google Inc. is seeking an RTL Design Engineer in Sunnyvale, CA to shape the future of AI/ML hardware acceleration. You will contribute to developing cutting-edge TPU technology and be part of a team innovating hardware solutions for Google's applications. The role requires...
$138k - $198k
...degree in Electrical Engineering, Computer Engineering,... ...experience in Physical Design (RTL-to-GDS) or Technology... ...Experience in scripting and automation using Tcl and Python (... .... Expertise in power integrity and reliability... ...to drive cutting‑edge TPU (Tensor Processing Unit...Worldwide- Google Inc. is seeking an experienced ASIC Design Engineer to help develop custom silicon solutions for its products. This role involves working... ...will have at least 8 years of experience with SystemVerilog RTL and a strong educational background in electrical engineering...Work at office
$138k - $198k
RTL Design Engineer, Machine Learning Accelerators corporate_fare Google place Sunnyvale, CA, USA... ...have an opportunity to drive cutting‑edge TPU (Tensor Processing Unit) technology... ...specific focus on TPU architecture and its integration within AI/ML‑driven systems. The AI...Full timeWorldwide$138k - $198k
Design Technology Co-Optimization Engineer Sunnyvale, CA, USA Qualifications Bachelor... ...Physical Design (RTL-to-GDS) or... ...Experience in scripting and automation using Tcl and... ...Expertise in power integrity and reliability analysis... ...drive cutting‑edge TPU technology that...Worldwide- Google Inc. in Sunnyvale, CA is seeking an experienced engineer for an ASIC design role focused on management and control subsystem design. The successful candidate will work on SystemVerilog RTL for ASIC products and collaborate with architecture, validation, and hardware...
- Google is looking for an experienced ASIC Design Engineer in Sunnyvale, California. In this role, you will take part in developing custom silicon... ...experience in digital design, particularly with SystemVerilog RTL. Competitive compensation includes a base salary of $163,000 -...
- Google Inc. in Sunnyvale, CA, is seeking an RTL Design Engineer to drive the next generation of AI accelerators. You will work on the design and implementation of custom silicon solutions for TPUs, the key hardware behind Google's innovative AI solutions. This role offers...
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