TPU RTL Design Engineer, Cloud

corporate_fare Google place Sunnyvale, CA, USA Qualifications Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 2 years of experience with RTL Design. Experience with digital design, including synchronous and asynchronous logic, state machines, and bus protocols. Experience optimizing designs for performance, power or area. Experience collaborating cross-functionally with DV teams on test plan creation and execution. Preferred qualifications Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture. Experience with CDC, RDC, RTL Linting and LEC. Experience with scripting languages (i.e. Tcl, Python or Perl). Experience architecting RTL solutions. About the role In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting‑edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML‑driven systems. As an RTL Design Engineer on the Tensor Processing Units (TPU) team, you will be a key contributor to the development of Google's AI accelerators. You will leverage your expertise in digital logic design, computer architecture, and RTL coding to create innovative and efficient hardware solutions. Responsibilities: Define and document the microarchitecture for digital designs within the TPU. Develop high-quality, performant, and power‑efficient Register Transfer Level (RTL) code, primarily in SystemVerilog. Collaborate with the verification team to develop test plans, debug RTL, and ensure functional correctness. Coordinate with the physical design team to meet timing, area, power, and manufacturability requirements. Contribute to the development and enhancement of design tools, flows, and methodologies. US: $138,000 - $198,000 (USD) + 15% bonus target + equity + benefits Google is proud to be an equal opportunity and affirmative action employer. We are committed to building a workforce that is representative of the users we serve, creating a culture of belonging, and providing an equal employment opportunity regardless of race, creed, color, religion, gender, sexual orientation, gender identity/expression, national origin, disability, age, genetic information, veteran status, marital status, pregnancy or related condition (including breastfeeding), expecting or parents‑to‑be, criminal histories consistent with legal requirements, or any other basis protected by law. See also Google's EEO Policy , Know your rights: workplace discrimination is illegal , Belonging at Google , and How we hire . Google is a global company and, in order to facilitate efficient collaboration and communication globally, English proficiency is a requirement for all roles unless stated otherwise in the job posting. Equity is granted exclusively and discretionally by Alphabet Inc. on the basis of an agreement concluded between you and Alphabet Inc. Alphabet Inc. is your sole contractual partner with respect to equity grants. GSU grants are not guaranteed, are discretionary, are subject to approval by the Alphabet Inc. board of directors or its delegate, the terms of the relevant Alphabet Inc. stock plan, and your grant agreement. They have no impact on statutory payments. Current or past grants do not confer an acquired right. #J-18808-Ljbffr Google Inc.