Principal ASIC Verification Engineer - Interface IP
Synopsys
Synopsys in Austin, Texas is seeking an experienced ASIC Digital Verification Engineer to ensure the highest quality in digital design. You will design verification environments for Interface IP protocols, create detailed test plans, and mentor junior engineers. The ideal candidate has extensive experience in ASIC digital verification, proficiency in SystemVerilog and UVM, and strong problem-solving skills. Join our innovative team and contribute to cutting-edge technologies that shape the future. #J-18808-Ljbffr Synopsys
Vacancy posted 4 days ago
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