Principal FPGA Design Engineer

Job Listings DV Engineer – IP Verification Location: Santa Clara, CA – 100% Remote. Responsibilities: Verify complex internal IP blocks such as compute engines, accelerators, and custom logic within SoC environments. Electrical Design Engineer – SoC Systems Responsibilities: Apply scientific methodologies and circuit design techniques to develop manufacturable products from a comprehensive integrated systems perspective. RTL Design Engineer – Verilog HDL Location: Santa Clara, CA. Responsibilities: Design RTL using Verilog HDL for implementation and debugging. Read and comprehend Analog Macro level architectural specifications. Model and characterize Analog-Mixed signals. FPGA-Based System Architect Responsibilities: Define FPGA‑centric system architectures for high‑throughput data processing platforms. Partition functionality across FPGA, ADC/DAC, and host interface components. ASIC Verification Engineer Location: San Jose, CA and Austin, TX (Day‑1 Onsite). Responsibilities: Execute synthesis, PNR, and STA for assigned partitions of ASIC chip adhering to strict schedules and design goals. Collaborate closely with architects, RTL designers, and DFT engineers. FPGA Design/Verification Engineer – Contract Requirements: Active security clearance is mandatory. Experience in aerospace, defense, aviation, or medical systems is preferred. Physical Design Engineer – SoC Projects Responsibilities: Support complex SoC projects for a client delivering advanced System‑on‑Chip solutions across multiple emerging technologies. Senior DV Engineer – Company Context Location: Santa Clara, CA. Responsibilities: Lead end‑to‑end engineering solutions across digital expertise domains. #J-18808-Ljbffr SiTime