Onsite RISC‑V CPU Internship - RTL/Verification
Tenstorrent
Tenstorrent is seeking interns to contribute to high-performance RISC‑V CPUs. You will work on RTL design, verification, and platform software, gaining hands-on experience with HDL design, CPU architecture, and tooling in a collaborative on-site setting. Ideal candidates are pursuing BS/MS/PhD in EE, ECE, CS, or CE with hands-on coursework or projects in CPU topics, Linux, and scripting. Roles span multiple sub-teams and locations, including Santa Clara. #J-18808-Ljbffr Tenstorrent
$86k - $170k
...seeking a New College Graduate CPU IP Design & Verification Engineer to join the MIPS... ...and verify advanced RISC-V processor IP. The role provides... ...microarchitecture, SystemVerilog RTL implementation, functional... .... Coursework, research, internship, or project experience with...InternshipFull timeLocal area$20 - $40 per hour
...more information, visit Internship Program Overview: Our Interns... ...Summary of Role: Join the MIPS CPU IP Engineering organization... ...in the design and verification of advanced RISC-V processor IP. You will work with CPU architects, RTL designers, and verification...InternshipWork experience placementSummer workLocal area$50 - $70 per hour
...developed a high performance RISC-V CPU from scratch, and... ...each sub-team does: RTL Design: Implement and... ...improvements. Design Verification: Verify high-performance... ...V CPUs. This role is onsite, based out of Austin,... ...Hiring Timelines This internship opportunity is...InternshipPermanent employmentWork experience placementSummer work$167.1k - $250.7k
## CPU Micro-Architecture and RTL Design Engineer (RISC-V)Santa Clara, California, United States of AmericaApply NowFind out how well you match with this jobJob... ..., performance, area and timing goals.* Functional verification support. Help the design verification team execute...SuggestedWork experience placementWork from home- ...Technologies, Inc. in Santa Clara, CA is seeking a CPU Micro-Architecture and RTL Design Engineer (RISC-V) to drive high-performance, low-power CPU design.... ...covers RTL ownership, architecture research, and verification support, with emphasis on timing, area, and reliability...Suggested
$167.1k - $250.7k
...*Job Area:**Engineering Group, Engineering Group CPU Engineering**General Summary:**As a Design Verification Engineer, you will work with Chip Architects to validate... ...Instruction Set Architectures, particularly RISC-V* Deep knowledge of Micro-Processor Verification functions...Work experience placementWork from home$167.1k - $250.7k
.... Job Area: Engineering Group, Engineering Group > CPU Engineering General Summary: As a Design Verification Engineer, you will work with Chip Architects to validate... ...Instruction Set Architectures, particularly RISC-V Deep knowledge of Micro-Processor Verification functions...Work experience placementWork from home$167.1k - $250.7k
...companion assembler library that together form the core of a RISC-V CPU design-verification toolchain. The RTG drives a JIT-style, simulator- coupled... ...knob-driven test profiles that compose objects to improve RTL coverage. Work within the privileged-software stack:...Work experience placementWork from home- ...company in Santa Clara, California is seeking a Design Verification Engineer to validate CPU and SOC micro-architectures. The ideal candidate will develop... .... Applicants should have extensive knowledge of RISC-V architecture and experience leading verification teams....
- Qualcomm is seeking a CPU-design verification engineer to contribute to a Python-based random test generation... ...and its assembler library, powering a RISC-V ISA verification toolchain. You will... ...interrupts. You will work with ISS and RTL teams to triage failures, craft...
$100k
...technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI... ...seniorities.We are looking for a Design Verification Engineer to contribute to the unit-level... ...Solver: Comfortable working alongside RTL designers to trace and fix...Permanent employment$167.1k - $250.7k
...Engineering Group, Engineering Group CPU Engineering General Summary:... ...-performance, production-grade RISC-V Instruction Set Simulator (ISS) that... ...The ISS is a key component of our verification flow: it drives co-simulation against RTL, powers random test generation, and...Work experience placementWork from home- SiFive, a leader in RISC-V technology, seeks a Staff Design Verification Engineer in Santa Clara to drive verification for high‑performance CPU cores and RVV vector extensions. You’ll define verification... ...and collaborate with architecture, RTL, and performance teams to ensure...
- ...Technologies, Inc. is building a high-performance RISC-V Instruction Set Simulator (ISS) used as the gold... .../execute flow, and drive co-simulation with RTL. The role blends architecture, systems software, and verification engineering with attention to bit-accurate correctness...
- ...As the pioneers who introduced RISC-V to the world, SiFive is transforming... ...is looking for a Staff Design Verification Engineer to drive verification of high-performance CPU core units. This is a Staff... ...work closely with architecture, RTL, performance, and verification...Immediate start
- ...As the pioneers who introduced RISC-V to the world, SiFive is transforming... ...is looking for a Staff Design Verification Engineer to drive verification of high-performance CPU core functionality, with... ...work closely with architecture, RTL, performance, and verification...Immediate start
- ...Technologies, Inc. in Cupertino seeks a verification engineer to contribute to a Python-based... ...and vector extensions. You will implement RISC-V extension generation objects, verify encodings... ...constraint-driven test themes to boost RTL coverage while collaborating with ISS/RTL...
- Qualcomm Technologies, Inc. is seeking a Design Verification Engineer in Austin, TX. You will work with CPU and SOC architects to validate micro-architectures, develop verification plans, and build scalable DV environments. You’ll create testbenches, checkers, and coverage...
$167.1k - $250.7k
...Engineering Group, Engineering Group CPU Engineering General Summary About... ...that together form the core of a RISC-V CPU design-verification toolchain. The RTG drives a JIT-style,... ...profiles that compose objects to improve RTL coverage. Work within the privileged...Work experience placementWork from home- ...hardware engineer to contribute to a Python-based random test generation framework and an assembler library that drive a RISC-V CPU design-verification toolchain. The RTG generates JIT-style, simulator-coupled test cases exercising the RVA23.1 ISA, including privileged...
- Qualcomm Technologies, Inc. seeks a skilled verification engineer to contribute to a Python-based... ...and a companion assembler library for a RISC-V CPU design-verification toolchain. You will... ...flows, and collaborate with ISS/RTL teams to triage #J-18808-Ljbffr QUALCOMM...
$198.7k - $298.1k
...Area:Engineering Group, Engineering Group > CPU EngineeringGeneral Summary:We are hiring talented engineers for RISCV CPU RTL development targeting high-performance, low... ..., area, and timing goalsSupport functional verification: assist the design verification team in...Work experience placementWork from home- ...Management/Reset/Clock Micro-Architect and RTL Design Engineer to pioneer PMU, clocking... ...power strategies for high-performance RISC-V CPU and SoC IP. You will work on highly-... ...generators, collaborating with architecture, verification, and software teams to deliver fast,...
$45 - $51 per hour
...Summary Rivian internships are experiences optimized... ...available to work onsite, full time (40... ...agents to automate RTL generation, code documentation... ...Develop tools and verification collateral for... ...architecture CPU and Memory... ...governance obligations; (v) recordkeeping; (vi...InternshipHourly payFull timeContract workSummer internshipLocal areaVisa sponsorshipShift work- ...As the pioneers who introduced RISC-V to the world, SiFive is transforming... ...is looking for a Senior Design Verification Engineer to drive verification of high-performance CPU core functionality, with... ...work closely with architecture, RTL, performance, and verification...
$167.1k - $250.7k
...General Summary We are hiring talented engineers for CPU RTL development targeted for high performance, low power devices. In this... ...power, performance, area and timing goals. Functional verification support. Help the design verification team execute on the functional...Work experience placementWork from home$140k - $300k
...up high performance, low-power CPU for next-generation compute... ...writing specifications and develop RTL for the CPU which targets and... ...configurable, and scalable. Verification - assist the verification team... ..., and area Experience with RISC-V or ARM64 or x86 ISA and their...Remote workFlexible hours$200k - $350k
...are looking for talented Design Verification Engineers to help verify and... ...work closely with architects, RTL engineers, software engineers... ...This role focuses on our custom CPU. We are designing a leading... ...Knowledge of the ARM or RISC-V instruction set architecture....Flexible hours- ...up high performance, low‑power CPU for next‑generation compute workloads. We are seeking Verification Engineers at multiple levels —... ...shoulder with architecture and RTL design. THE ROLE Plan & Strategy... ...one modern ISA (x86, ARM, or RISC‑V). Hands‑on functional verification...
$231.44k - $282.88k
...As the pioneers who introduced RISC-V to the world, SiFive is... ...looking for a Principal Design Verification Engineer to lead verification... ...subsystem used in high-performance CPU and SoC platforms. This is a principal... ...work across architecture, RTL, formal, performance, and...Work experience placement
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