Senior Design Verification Engineer

Job Details Intel is seeking a Senior Design Verification Engineer for the Silicon Chassis team. In this role, you will own end-to-end verification of critical chassis and interconnect IP blocks from planning through signoff. You will drive quality in testbench architecture, test plan and coverage closure while working closely with architecture, design, and software teams. This position requires strong technical depth in DV methodologies, protocol verification, and memory subsystem behavior, with enough breadth in RTL, physical design, and CAD to contribute across traditional discipline boundaries. AI-assisted workflows are part of everyday development here. Consistent execution against schedule and quality goals is expected. Responsibilities Own verification planning and execution for key IP features across IP and subsystem integration points. Build scalable verification environments and targeted test plans with reusable test benches, checkers, VIPs, and behavioral models. Collaborate closely with architecture, design, and software teams from specification through bringup; contribute across role boundaries when needed to unblock progress and maintain execution quality. Drive ownership of multiple critical blocks and verification components; take full responsibility for functional signoffs and achievement of performance and power metrics. Lead IP delivery to multiple customers while ensuring technical excellence; balance competing requirements, schedules, and resources across teams. Drive convergence of simulation and formal verification into unified bug hunting and coverage closure strategies; evaluate and adopt emerging methodologies including ML-driven verification flows. Mentor and develop verification engineers; establish verification best practices and raise team-level execution quality. Comfortable using AI-assisted development tools as part of everyday workflow; track record of delivering reusable, configurable verification collateral. Qualifications Bachelor of Science Degree in Electrical or Computer Engineering, Computer Science, or a STEM related field. 10+ years of experience in design verification (DV); with extensive background in IP DV and subsystem and SoC-level verification. Experience in interconnects, caches, and memory subsystems, including multiple bus protocols such as AMBA (CHI, ACE, AXI), PCIe, UCIe, and CXL; cache coherency and memory consistency models. Experience in verification of global functions including debug, trace, clock and power management, RAS, QoS, and security feature. Experience in simulation and formal verification methodologies including UVM, SVA, ABV, and co-simulation; proficiency in low-power verification techniques, HDL/verification languages, and industry-standard EDA tools. Hands‑on coding experience across SystemVerilog/UVM, C/C++, Python, and build systems. Experience working with RTL, physical design, and CAD tool flows; contribute outside core DV responsibilities as needed. Post‑graduate degree in Electrical or Computer Engineering, Computer Science, or a STEM related field (preferred). Experience with formal verification tools (JasperGold, VC Formal, or similar) and emulation or FPGA‑based verification; track record of combining formal and simulation for unified bug closure (preferred). Prior work with system IPs such as MMUs (SMMU or IOMMU) and interrupt controllers, and working knowledge of the associated software stacks (preferred). Job Type and Location Experienced Hire. Shift: Shift 1 (United States of America). Primary Location: US, California, Santa Clara. Posting Statement All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Benefits We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Salary Range Annual Salary Range for jobs which could be performed in the US: $164,470.00‑311,890.00 USD. #J-18808-Ljbffr