Design Verification Engineer

Job Details: Job Description: The Role and Impact As an IP Design Verification Engineer, you will play a pivotal role in Intel's mission to advance cutting-edge technology. You will ensure that Intel's intellectual property (IP) designs meet rigorous quality standards, delivering robust and reliable solutions that power the innovations of tomorrow. In this role, you will collaborate with cross-functional teams to verify and validate complex architectural and microarchitectural features, contributing to Intel's industry leadership in hardware design and development. Your work will directly impact the performance, power efficiency, and reliability of next-generation computing systems, shaping the future of technology. Key Responsibilities Develop and execute comprehensive IP verification plans to ensure compliance with microarchitecture specifications. Design, implement, and maintain test benches and verification environments to achieve optimal coverage. Define and run system simulation models to verify IP design functionality, analyze power and timing, and identify bugs. Debug, root cause, and resolve pre-silicon design issues, implementing corrective measures for test failures. Collaborate with architects, RTL developers, and physical design teams to enhance the verification process for complex designs. Document verification plans and present technical reviews to design and architecture teams. Maintain and improve functional verification infrastructure, methodologies, and related workflows. Contribute to the definition and refinement of verification infrastructure and test framework methodologies (TFMs). Qualifications Minimum Qualifications: Bachelor's degree in electrical engineering, Computer Engineering or computer science or a related technical discipline and 6 or more years of relevant experience; or master's degree with 4 or more years of experience; or PhD with 2 or more years of experience. 3+ years with the following technical skills: Proficiency in System Verilog with a strong understanding of OVM and UVM methodologies. Experience in functional verification of IP designs, including debugging and root cause analysis. Hands‑on expertise with digital design fundamentals, hardware simulation, and verification tools. Demonstrated experience in developing test content, validation tools, and methodologies. Solid knowledge of microarchitecture, hardware design, and power/performance validation. Preferred Qualifications Knowledge of DDR/LPDDR and DFI protocol and validation. Experience in DDR PHY validation. Proven ability to work collaboratively in cross‑functional teams and previous experience driving technical reviews. Strong analytical and problem‑solving skills, with a focus on identifying bugs and implementing effective solutions. Familiarity with formal verification methods and IP microarchitecture validation. Knowledge of hardware architecture and its integration into larger systems. Exposure to performance‑driven design validation and optimization techniques. Posting Statement All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Annual Salary Range For jobs which could be performed in the US: $141,910.00-269,100.00 USD. #J-18808-Ljbffr