SoC DV Engineer - Verilog, UVM & Testbench Expert
Apple Inc.
Apple Inc. in Cupertino, CA is seeking a Design Verification Engineer to verify functionality and performance of Apple's premier SOCs. You will review design specs, test benches, and work with design, architecture, and software teams to drive verification coverage. The role requires a BS + 3+ years experience, strong knowledge of Verilog/SystemVerilog, digital design fundamentals, and scripting (Python/Perl). #J-18808-Ljbffr Apple Inc.
Vacancy posted 3 days ago
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