Senior Physical Design Engineer - PnR, PPA & Timing
Wipro
Wipro is seeking a Physical Design Engineer to lead PD/PNR activities in Mountain View. You will drive block-level implementation from netlist to GDSII, including floorplanning, CTS, routing, power planning, and verification, with emphasis on PPA, timing convergence, and signoff. The role requires 8–10 years of experience in VLSI physical design, strong debugging skills, and collaboration with RTL/DFT/STA teams. Eligible for Wipro’s broad benefits and equal opportunity employer policy. #J-18808-Ljbffr Wipro
Vacancy posted 5 days ago
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