ASIC Design Verification Engineer, TPU Cloud Compute

corporate_fare Google place Sunnyvale, CA, USA Qualifications Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 4 years of experience with design verification. Experience with SystemVerilog/Verilog. Preferred Qualifications Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture. 5 years of experience with industry standard tools, languages and methodologies relevant to the development of silicon-based individual contributors (ICs) and chips. Experience in the full verification life-cycle from test planning to coverage closure. Experience with 2 or more SoC projects/cycles. Experience in verifying digital logic at RTL using SystemVerilog/UVM for ASICs. Familiarity with ASIC standard interfaces and memory system architecture. About the Job In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting‑edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML‑driven systems. As an ASIC Design Verification Engineer, you will be part of a team developing ASICs used to accelerate computation in data centers. You will have dynamic, multi‑faceted responsibilities in areas such as project definition, design verification and silicon bring‑up. You will participate in the architecture, documentation, and verification of the next generation of data center accelerators. Responsibilities Plan the verification of complex digital design blocks by understanding the design specification and interacting with design engineers to identify important verification scenarios. Create a constrained‑random verification environment using SystemVerilog and Universal Verification Methodology (UVM). Identify and write all types of coverage measures for stimulus and corner‑cases. Debug tests with design engineers to deliver functionally correct design blocks. Close coverage measures to identify verification holes and to show progress towards tape‑out. US: $138000 - $198000 (USD) + 15% bonus target + equity + benefits Google is proud to be an equal opportunity and affirmative action employer. We are committed to building a workforce that is representative of the users we serve, creating a culture of belonging, and providing an equal employment opportunity regardless of race, creed, color, religion, gender, sexual orientation, gender identity/expression, national origin, disability, age, genetic information, veteran status, marital status, pregnancy or related condition (including breastfeeding), expecting or parents‑to‑be, criminal histories consistent with legal requirements, or any other basis protected by law. See also Google's EEO Policy, Know your rights: workplace discrimination is illegal, Belonging at Google, and How we hire. Google is a global company and, in order to facilitate efficient collaboration and communication globally, English proficiency is a requirement for all roles unless stated otherwise in the job posting. #J-18808-Ljbffr Google Inc.