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Principal SOC Design Engineer - Clocking & Verification

Jobleads-US

Cadence Design Systems in San Jose is seeking a Principal Design Engineer to lead SOC/sub-system projects, drive timing closure, and oversee physical verification for tape-out readiness. You will collaborate with Front End RTL and Back End teams to optimize RTL synthesis, floor planning, clock trees, and power integrity.

The ideal candidate has Cadence tool expertise (Innovus, Tempus, QRC, Voltus, Pegasus), strong leadership, and hands-on experience with advanced nodes and PCIe/DDR interfaces.

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Vacancy posted 3 days ago
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