RTL Design Tech Lead - AI Hardware Connectivity
Socket.dev
Astera Labs in California is hiring a Tech Lead Design Engineer to architect and deliver connectivity silicon for AI clusters. You will own RTL design from microarchitecture to tapeout and work with architecture, verification, DFT, and physical design teams. This high-impact role requires 5+ years in digital design, strong Verilog/SystemVerilog skills, and experience with high-speed interfaces. Leadership and mentoring are key, with opportunities to influence tapeout schedules and design #J-18808-Ljbffr Socket.dev
Vacancy posted 4 days ago
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